Search Results - "KERKHOFF, H. G"

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    A new test generation approach for embedded analogue cores in SoC by Stancic, M., Fang, L., Weusthof, M.H.H., Tijink, R.M.W., Kerkhoff, H.G.

    “…This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis…”
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    Conference Proceeding
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    Testability analysis of analog systems by Hemink, G.J., Meijer, B.W., Kerkhoff, H.G.

    “…A method is presented to analyze the testability of both linear and nonlinear analog systems. It combines a rank-test algorithm with statistical methods. The…”
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    Journal Article
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    Testable design and testing of micro-electro-fluidic arrays by Kerkhoff, H.G., Acar, M.

    “…The testable design and testing of a fully software-controllable lab-on-a-chip, including a fluidic array of FlowFETs, control and interface electronics is…”
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    Conference Proceeding
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    On the maximization of the sustained switching activity in a processor by Cantoro, R., Reorda, M. Sonza, Rohani, A., Kerkhoff, H. G.

    “…Recently, several application areas in the test domain (e.g., burn-in and aging monitoring) started to require suitable input stimuli, able to maximize the…”
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    Conference Proceeding
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    Defect-oriented testing of Josephson logic circuits and systems by Kerkhoff, H.G., Speek, H.

    Published in Physica. C, Superconductivity (15-02-2001)
    “…In this paper, defect-oriented testing of low temperature superconducting Josephson logic systems is used as a basis for structural test generation. This…”
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    Journal Article
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    Testing of a microanalysis system by Kerkhoff, H.G.

    “…During the testing of microsystems, one has to cope with many problems resulting from inaccessibility, different technologies, and nonelectrical failure modes…”
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    Journal Article
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    Computer-aided test flow in core-based design by Zivkovic, V.A, Tangelder, R.J.W.T, Kerkhoff, H.G

    Published in Microelectronics (01-12-2000)
    “…This paper copes with the efficient test-pattern generation in a core-based design. A consistent Computer-Aided Test (CAT) flow is proposed based on the…”
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    Journal Article
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    Structural testing of the HYPRES niobium process by Joseph, A.A., Sese, J., Flokstra, J., Kerkhoff, H.G.

    “…The HYPRES 3.0 /spl mu/m niobium (Nb) process has proven to be capable of realizing complex low temperature superconductor (LTS) rapid single flux quantum…”
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    Journal Article Conference Proceeding
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    Test structures and their application in structural testing of digital RSFQ circuits by Joseph, Arun A., Heuvelmans, Sander, Gerritsma, Gerrit J., Kerkhoff, Hans G.

    Published in Physica. C, Superconductivity (15-03-2004)
    “…As the niobium (Nb) LTS RSFQ processes advance being the technology for future ultrahigh-speed systems in the digital domain, the quality of the process should…”
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    Journal Article
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    The detection of defects in a niobium tri-layer process by Joseph, A.A., Heuvelmans, S., Gerritsma, G.J., Kerkhoff, H.G.

    “…Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson…”
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    Journal Article Conference Proceeding
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    VHDL-AMS fault simulation for testing DNA bio-sensing arrays by Kerkhoff, H.G., Zhang, X., Liu, H., Richardson, A., Nouet, P., Azais, F.

    Published in IEEE Sensors, 2005 (2005)
    “…The market of microelectronic fluidic arrays for biomedical applications, like DNA determination, is rapidly increasing. In order to evaluate these systems in…”
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    Conference Proceeding
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    On-line dependability enhancement of multiprocessor SoCs by resource management by Ter Braak, T D, Burgess, S T, Hurskainen, H, Kerkhoff, H G, Vermeulen, B, Zhang, X

    “…This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the…”
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    Conference Proceeding
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    On-chip tap-delay measurements for a digital delay-line used in high-speed inter-chip data communications by Petre, O., Kerkhoff, H.G.

    “…During the last few years, new synchronization techniques to send data between ICs at increasingly high data-rates have been developed. Some of them rely on…”
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    Conference Proceeding
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    An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures by Zivkovic, Va, Tangelder, Rjwt, Kerkhoff, Hg

    Published in Journal of electronic testing (01-04-2002)
    “…In this paper the implementation of the test strategy in a so-called Very Long Instruction Word Transport Triggered Architecture (VLIW-TTA) is discussed. The…”
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    Journal Article