Search Results - "KASAI, Kunihiro"

Low-resistivity poly-metal gate electrode durable for high-temperature processing by Akasaka, Y., Suehiro, S., Nakajima, K., Nakasugi, T., Miyano, K., Kasai, K., Oyamatsu, H., Kinugawa, M., Takagi, M.T., Agawa, K., Matsuoka, F., Kakumu, M., Suguro, K.

“…A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100…”
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Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET by Matsuoka, F., Kasai, K., Oyamatsu, H., Kinugawa, M., Maeguchi, K.

“…A guideline for n/sup /spl minus// fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, the greatest…”
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A highly manufacturable high density embedded SRAM technology for 90nm CMOS by FUKAURA, Yasuhiro, KASAI, Kunihiro, OKAYAMA, Yasunori, KAWASAKI, Hirohisa, ISOBE, Kazuaki, KANDA, Masahiko, ISHIMARU, Kazunari, ISHIUCHI, Hidemi

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Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si1-xGex virtual substrate by KAWASAKI, Hirohisa, OHUCHI, Kazuya, AOKI, Nobutoshi, KANEMURA, Takahisa, HAGISHNW, Daisuke, FUJIWARA, Makoto, INABA, Satoshi, ISHIRNARU, Kazunari, NAGASHIMA, Naoki, ISHIUCHI, Hidemi, OISHI, Amane, FUJII, Osamu, TSUJII, Hideji, ISHIDA, Tatsuya, KASAI, Kunihiro, OKAYAMA, Yasunori, KOJIMA, Kenji, ADACHI, Kanna

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