Search Results - "K.P. Pradhan"

Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential by K.P. Pradhan, M.R. Kumar, S.K. Mohapatra, P.K. Sahu

“…In this paper, an analytical threshold voltage model is proposed for a cylindrical gate-all-around (CGAA) MOSFET by solving the 2-D Poisson’s equation in the…”
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Towards the Development of Unified Models for Memristors: Charge-Flux Relationship by Pranavi, A.N., Dixit, Tejendra, Pradhan, K.P.

“…Memristors have garnered the great attention of the scientific community due to the immense scope in memory technology and neuromorphic computing. Like any…”
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Memoryless linearity in undoped and B-doped graphene FETs: A relative investigation to report improved reliability by Chandrasekar, L., Pradhan, K.P.

“…In this work, reliability of boron-doped graphene field effect transistor (GFET) is examined by modeling the effect of doping in terms of linearity performance…”
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Performance limitation of Cu2FeSnS4 solar cell: Understanding impact of density of defect states by Varku, Shibi, Pradhan, K.P., Routray, S.

“…Copper based quaternary chalcogenides such as Cu2ZnSnSe4 (CZTSe), Cu2ZnSnS4(CZTS), Cu2ZnSn(SxSe1−x)4, Cu2FeSnS4 (CFTS) have become area of research interest…”
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Loss mechanisms in CZTS and CZTSe Kesterite thin-film solar cells: Understanding the complexity of defect density by Sravani, L., Routray, S., Courel, Maykel, Pradhan, K.P.

“…•Performance evaluation of Kesterite solar cell without defects and trap charges.•Analysis of kesterite solar cell in presence of Defect densities and trap…”
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Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications by Mallikarjunarao, Ranjan, Rajeev, Pradhan, K.P., Artola, L., Sahu, P.K.

“…In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for…”
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Impact of unpreventable induced interface trapped charges on HZO based FDSOI NCFET by Seshu, Vullakula Rama, Shaik, Rameez Raja, Pradhan, K.P.

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Is accumulation or inversion mode dielectric modulated FET better for label-free biosensing?: A comparative investigation by Sariki, Akhil, Venkata Rao, K., Chandrasekar, L., Shaik, Rameez Raja, Pradhan, K.P.

“…In this paper, we present a comprehensive assessment of dielectric modulated accumulation mode field-effect transistor (AMFET) architecture for label-free…”
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Memoryless nonlinearity in IT JL FinFET with spacer technology: Investigation towards reliability by Vandana, B., Mohapatra, S.K., Das, J.K., Pradhan, K.P., Kundu, A., Kaushik, B.K.

“…This work investigates the reliability assessment of high-k spacer and the effect of temperature on the device analog/RF performance for Inverted ‘T' (IT)…”
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Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET by Mohapatra, S.K., Pradhan, K.P., Artola, L., Sahu, P.K.

“…In this paper, the analog performance as well as some new RF figures of merit (FOMs) are reported for the first time of a gate stack double gate (GS-DG) metal…”
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Investigating single event transients of advanced fin based devices for inclusion in ICs by Dimri, Chinmay, Nikhil, G.P., Mohanty, P.K., Pradhan, K.P., Agarwal, R., Routray, S.

“…In the present work, various 10 nm FD-SOI FinFET structures utilizing promising design elements like raised source and drain extensions, hybrid air spacer, and…”
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Device and circuit performance of Si-based accumulation-mode CGAA CMOS inverter by Ranjan Panda, Soumya, Pradhan, K.P., Sahu, P.K.

“…This paper presents a detailed investigation of the static and Mixed−Mode analysis of the accumulation-mode cylindrical gate all around (AM-CGAA) MOSFET…”
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Zero temperature-coefficient bias point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges by Sahu, P.K., Mohapatra, S.K., Pradhan, K.P.

“…This paper is a unique attempt to identify the zero-temperature-coefficient (ZTC) point and other performance metrics for single gate (SG), double gate (DG),…”
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Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs by Pradhan, K.P., Priyanka, Sahu, P.K.

“…Symmetric Dual-k Spacer (SDS) Hybrid FinFETs is a novel device, which combines three significant technologies i.e., 2-D ultra-thin-body (UTB), 3-D FinFET, and…”
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Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET by Pradhan, K.P., Mohapatra, S.K., Sahu, P.K., Behera, D.K.

“…Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO2) based gate dielectric for nanoscale semiconductor devices…”
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Back-gate bias effect on the linearity of pocket doped FDSOI MOSFET by Shaik, Rameez Raja, Chandrasekar, L., Raskin, Jean-Pierre, Pradhan, K.P.

“…In this article, we investigate the feasibility of enhancing the linearity Figures of Merit (FoMs) by introducing pocket implant in the source/drain regions of…”
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Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application by Pradhan, K.P., Priyanka, Mallikarjunarao, Sahu, P.K.

“…This paper evaluates the novelty aspects of symmetric high-k spacer (SHS) hybrid FinFET over conventional FinFET. The SHS hybrid FinFET combines three…”
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Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET by Pradhan, K.P., Priyanka, Sahu, P.K.

“…Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body…”
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Dielectric engineered symmetric underlap double gate tunnel FET (DGTFET): An investigation towards variation of dielectric materials by Mallikarjunarao, Ranjan, Rajeev, Pradhan, K.P., Sahu, P.K.

“…In this article, an underlap silicon n-channel Tunnel Field Effect Transistor (n-TFET) i.e., symmetric single-k spacer (SSS) Double Gate N-TFET (DGTFET) is…”
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Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics by Mohapatra, S.K., Pradhan, K.P., Sahu, P.K.

“…•An attempt to characterization of TCP/ZTC point of UT-SDOI SG, DG and GS-DG, n-MOSFET.•The interface trapped charges during the pre and post fabrications…”
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