Search Results - "Joy, S.P."

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  1. 1

    High-resolution shape model of Ceres from stereophotoclinometry using Dawn Imaging Data by Park, R.S., Vaughan, A.T., Konopliv, A.S., Ermakov, A.I., Mastrodemos, N., Castillo-Rogez, J.C., Joy, S.P., Nathues, A., Polanskey, C.A., Rayman, M.D., Riedel, J.E., Raymond, C.A., Russell, C.T., Zuber, M.T.

    Published in Icarus (New York, N.Y. 1962) (01-02-2019)
    “…•Processed ∼38,000 images acquired by the Dawn spacecraft to determine Ceres’ shape.•High-resolution global shape of Ceres was determined using…”
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    Journal Article
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    Large scale changes in the highly energetic charged particles in the region of the Io torus by Russell, C.T., Fieseler, P.D., Bindshadler, D., Yu, Z.J., Joy, S.P., Khurana, K.K., Kivelson, M.G.

    Published in Advances in space research (01-01-2001)
    “…The Galileo star sensor is heavily shielded from penetrating radiation to prevent false counts. Nevertheless in the inner jovian magnetosphere the penetrating…”
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    Journal Article
  4. 4

    Stochastic logic computation based RBFNN with adaptive hidden layer structure by S.P. Joy Vasantha Rani, Prabha, K Aruna

    “…Purpose - The purpose of this paper is to implement the hardware structure for radial basis function (RBF) neural network based on stochastic logic…”
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    Journal Article
  5. 5

    Novel cat swarm optimization algorithm to enhance channel equalization by Diana, D C, Joy Vasantha Rani SP

    Published in Compel (01-01-2017)
    “…Purpose Adaptive equalization plays an important role in digital communication to reduce the distortions due to inter-symbol interference. An adaptive filter…”
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    Journal Article
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    Voltage Controlled PFC Based Interleaved Synchronous Buck Converter BLDC motor by Rajamani, Thangam, Vasantha, Rani S.P Joy

    “…In this work power factor improvement and harmonic minimization for the interleaved synchronous buck converter connected through the nonlinear load is…”
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    Conference Proceeding
  8. 8

    Design of Logic Blocks for Efficient Architecture of FPGA by Sudhanya, P., Rani, S.P. Joy Vasantha, Lavanya, M.C.

    “…This paper analyses different hybrid logic blocks composed of Look-Up Tables (LUTs) and Universal Logic Gates (ULGs). The pure LUT based architecture incurs a…”
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    Conference Proceeding
  9. 9

    Design of linear ramp generator for ADC by Ashwini, S., Sivakumar, M. Senthil, Vasantha Rani, S.P. Joy

    “…In recent years, the electronic systems become more complex due to high integration of multi-system functionalities with deep submicron technologies. Also, the…”
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    Conference Proceeding
  10. 10

    A VLSI implementation of an adaptive genetic algorithm processor by Jayashree, M., Ranjith, C., Vasantha Rani, S.P. Joy

    “…A genetic algorithm (GA) is a powerful heuristic method of selection based on natural living process. Because of larger size of the scheduling, implementing GA…”
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    Conference Proceeding
  11. 11

    Multilayer Perceptron Neural Network Architecture using VHDL with Combinational Logic Sigmoid Function by Joy Vasantha Rani, S.P., Kanagasabapathy, P.

    “…This paper presents the hardware realization of fast and flexible feed forward neural network which is capable of dealing with fixed point arithmetic…”
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    Conference Proceeding