Search Results - "Joo Tae Moon"
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Fabrication and Device Characterization of Omega-Shaped-Gate ZnO Nanowire Field-Effect Transistors
Published in Nano letters (01-07-2006)“…Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have attracted a great deal of attention recently, because theoretical simulations…”
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Experimental investigation of the impact of LWR on sub-100-nm device performance
Published in IEEE transactions on electron devices (01-12-2004)“…Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a…”
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Selective growth of carbon nanotube for via interconnects by oxidation and selective reduction of catalyst
Published in Applied physics letters (03-11-2008)“…We propose a selective growth approach of carbon nanotubes (CNTs) to prevent interface rupture in CNT via interconnects. Oxidation of the Ni catalyst layer is…”
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Etching characteristics and modeling for oval-shaped contact
Published in Thin solid films (23-04-2007)“…In this study, etching characteristics of oval-shaped contact were investigated. The oval-shaped contact showed different etching characteristics compared to…”
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Journal Article Conference Proceeding -
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Spatial Distribution of Interface Traps in Sub-50-nm Recess-Channel-Type DRAM Cell Transistors
Published in IEEE electron device letters (01-01-2011)“…The spatial distribution of the interface traps in dynamic random access memory (DRAM) cell transistors having deeply recessed channels for sub-50-nm…”
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Leakage Current Reduction Mechanism of Oxide--Nitride--Oxide Inter-Poly Dielectrics through the Post Plasma Oxidation Treatment
Published in Japanese Journal of Applied Physics (01-04-2011)“…High quality oxide--nitride--oxide (ONO) inter-poly dielectrics were successfully fabricated by the optimized plasma oxidation without H 2 . The bottom low…”
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Low-Temperature Solid Phase Epitaxial Regrowth of Silicon for Stacked Static Random Memory Application
Published in Japanese Journal of Applied Physics (01-01-2011)“…Solid phase epitaxy (SPE) techniques have been studied to realize stacked static random memory (SRAM) devices. Among the candidates including epitaxial lateral…”
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Characterization of threshold voltage instability after program in charge trap flash memory
Published in 2009 IEEE International Reliability Physics Symposium (01-04-2009)“…We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage…”
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Conference Proceeding
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Effect of pre-existing void in sub-30nm Cu interconnect reliability
Published in 2010 IEEE International Reliability Physics Symposium (01-01-2010)“…Pre-existing void effect during electromigration in a sub-30nm wide Cu interconnect was observed. Two types of void are intentionally produced in a single…”
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Conference Proceeding -
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Gate oxide effect on wafer level reliability of next generation dram transistors
Published in 2010 IEEE International Reliability Physics Symposium (01-05-2010)“…Wafer level reliability (WLR) issues of DRAM cell and peripheral transistors are discussed. Since the 70 nm technology node, recessed transistors have been…”
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Conference Proceeding -
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Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)
Published in 2009 Symposium on VLSI Technology (01-06-2009)“…A novel 3-D NAND flash memory device, VSAT (Vertical-Stacked-Array-Transistor), has successfully been achieved. The VSAT was realized through a cost-effective…”
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Conference Proceeding -
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Electromigration tests for critical stress and failure mechanism evaluation in Cu/W via/Al hybrid interconnect
Published in 2009 IEEE International Reliability Physics Symposium (01-04-2009)“…Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between…”
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Conference Proceeding -
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Electrical field dependence of data retention in high-k interpoly dielectrics
Published in 2009 IEEE International Reliability Physics Symposium (01-04-2009)“…Data retention characteristics of aggressively scaled high-k interpoly dielectrics (IPD) with a fully planar stacked cell are thoroughly investigated. Using…”
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Conference Proceeding -
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Most Efficient Alternative Manner of Patterning sub-80 nm Contact Holes and Trenches with 193 nm Lithography
Published in Japanese Journal of Applied Physics (01-06-2004)“…The patterning of sub-80 nm contact holes and trenches by ArF lithography is very challenging. To solve this problem, several technologies have been proposed,…”
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State of the art technologies and future prospective in display industry
Published in 2012 International Electron Devices Meeting (01-12-2012)“…The ultimate purpose of a display is hyper-realistic regeneration of the physical experience that mankind enjoys every day. The two main characteristics…”
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Conference Proceeding -
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High temperature platinum etching using Ti mask layer
Published in Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films (01-07-1999)“…Platinum is a strong candidate for an electrode material of the high dielectric capacitors in highly integrated dynamic random access memory devices. However,…”
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Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance
Published in Japanese Journal of Applied Physics (01-06-2005)“…The improved contact resistance was obtained by the new barrier metal scheme such as CVD-Co/Ti/TiN process in the level of about half of that from CVD-Ti/TiN…”
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Improved Cell Performance for sub-50 nm DRAM with Manufacturable Bulk FinFET Structure
Published in 2007 IEEE Symposium on VLSI Technology (01-06-2007)“…FinFET, the milestone for sub-50 nm DRAM cell transistor has been successfully demonstrated by a unique fabricating method with novel concept. We obtained a…”
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Conference Proceeding -
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Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes
Published in Solid-state electronics (01-02-2011)“…We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50 nm technology using a…”
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