Search Results - "Joo, Hansung"

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  1. 1
    A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

    A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth by Youngdon Choi, Ickhyun Song, Mu-Hui Park, Hoeju Chung, Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Duckmin Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, Min Gu Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaehwan Kim, Yong-Jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, Horii, Hideki, Jaewook Lee, Kisung Kim, Hansung Joo, Kwangjin Lee, Yeong-Taek Lee, Jeihwan Yoo, Jeong, G.

    “…Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and…”
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  2. 2
    A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications

    A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications by Hyun-Jin Kim, Youngdon Choi, Jangwoo Lee, Jindo Byun, Seungwoo Yu, Daehoon Na, Jungjune Park, Kwangwon Kim, Kavala, Anil, Youngmin Jo, Changbum Kim, Sunghoon Kim, Nahyun Kim, Jaehwan Kim, Bongkil Jung, Yena Lee, Chanjin Park, Hansung Joo, Kisung Kim, Yunhee Choi, Pansuk Kwak, Hyeonggon Kim, Jeong-Don Ihm, Dae-Seok Byeon, Jin-Yub Lee, Ki-Tae Park, Kye-Hyun Kyung

    Published in 2017 Symposium on VLSI Circuits (01-06-2017)
    “…A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the…”
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  3. 3
    Experimental observation of the post-annealing effect on the dark current of InGaAs waveguide photodiodes

    Experimental observation of the post-annealing effect on the dark current of InGaAs waveguide photodiodes by Joo, Hansung, Jeon, Su Chang, Kwon, Yong Hwan, Choe, Joong-Seon, Yun, Ilgu

    Published in Solid-state electronics (01-09-2006)
    “…The post-annealing effect on the dark current of the InGaAs waveguide photodiodes, which are developed for 40-Gbps optical receiver applications, is…”
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  4. 4
    Dynamic Vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories

    Dynamic Vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories by Park, Ki-Tae, Kang, Myounggon, Hwang, Soonwook, Song, Youngsun, Lee, Jaewook, Joo, Hansung, Oh, Hyun-Sil, Kim, Jae-ho, Lee, Yeong-taek, Kim, Changhyun, Lee, Wonseong

    Published in 2009 Symposium on VLSI Circuits (01-06-2009)
    “…In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase cells are presented for achieving high program inhibition of sub-40nm MLC NAND flash and…”
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