Evidence of Interface Trap Build-Up in Irradiated 14-nm Bulk FinFET Technologies

Evidence of Interface Trap Build-Up in Irradiated 14-nm Bulk FinFET Technologies

Total ionizing dose response of 14-nm bulk-Si FinFETs has been studied with a specially designed test chip. The radiation testing shows evidence of interface trap build-up on 14-nm Bulk FinFET technologies. These defects created in the isolation layer give rise to a new radiation-induced leakage pat...

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Bibliographic Details
Published in:IEEE transactions on nuclear science Vol. 68; no. 5; pp. 671 - 676
Main Authors: Privat, A., Barnaby, H. J., Spear, M., Esposito, M., Manuel, J. E., Clark, L., Brunhaver, J., Duvnjak, A., Jokai, R., Holbert, K. E., McLain, M. L., Marinella, M. J., King, M. P.
Format: Journal Article
Language:English
Published: New York IEEE 01-05-2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
14-nm bulk technology
Accumulation
CMOS
device modeling
Doping
FinFET
FinFETs
interface traps
Inverters
Leakage current
Logic gates
Mathematical models
Performance evaluation
Radiation
Radiation effects
Radiation leaks
TCAD
Three-dimensional displays
total ionizing dose
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Summary:Total ionizing dose response of 14-nm bulk-Si FinFETs has been studied with a specially designed test chip. The radiation testing shows evidence of interface trap build-up on 14-nm Bulk FinFET technologies. These defects created in the isolation layer give rise to a new radiation-induced leakage path which might lead to a reliability issue in CMOS technologies at or below the 14-nm node. TCAD simulations are performed and an analytical model for TID-induced leakage current is presented to support analysis of the identified TID mechanism. TCAD simulation and analytical model results are consistent with the experimental data.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2021.3065267