Impact of gate workfunction on device performance at the 50 nm technology node
The optimal gate electrode workfunction was determined for the 50 nm technology node using a simulation strategy that takes into account the impact of short-channel effects on device performance in uniformly doped and super-steep-retrograde doped channels in conventional and dynamic threshold operat...
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| Published in: | Solid-state electronics Vol. 44; no. 6; pp. 1077 - 1080 |
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| Main Authors: | , , , |
| Format: | Journal Article |
| Language: | English |
| Published: |
Elsevier Ltd
01-06-2000
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| Subjects: | |
| Online Access: | Get full text |
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| Summary: | The optimal gate electrode workfunction was determined for the 50 nm technology node using a simulation strategy that takes into account the impact of short-channel effects on device performance in uniformly doped and super-steep-retrograde doped channels in conventional and dynamic threshold operation. Classical device simulations suggest that the optimal workfunction is such that the gate Fermi level is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS) devices. However, when quantum mechanical effects are taken into account, the optimal workfunction is such that the gate Fermi level coincides with the conduction (valence) band edge. Midgap gates are not viable because the resulting short-channel effects are too severe. In a surrounding-gate transistor the optimal workfunction is attained when the gate Fermi level is 0.35 eV below (above) the conduction (valence) band edge in NMOS (PMOS) device. Midgap gates are not viable because the resulting threshold voltage is too high and cannot be reduced by lowering the substrate doping. |
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| Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
| ISSN: | 0038-1101 1879-2405 |
| DOI: | 10.1016/S0038-1101(99)00323-8 |