A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

This article presents a novel method for frequency tracking based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely covers the tuning range of the digitally controlled osc...

Full description

Saved in:

Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 55; no. 10; pp. 2831 - 2841
Main Authors:	Yu, Changzhi, Sa, Euije, Jin, Soowan, Park, Himchan, Shin, Jongshin, Burm, Jinwook
Format:	Journal Article
Language:	English
Published:	New York IEEE 01-10-2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Circuits Clock recovery Clocks CMOS Data recovery Detectors Digital filters Digital loop filter digitally controlled oscillator (DCO) extended bang-bang phase detector (XBBPD) Frequency locking half-rate sampling high-speed integrated circuits Oscillators Phase detectors Phase frequency detector Power consumption Receivers referenceless clock and data recovery (CDR) Time-frequency analysis Timing Tracking Vibration
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Description
Summary:	This article presents a novel method for frequency tracking based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely covers the tuning range of the digitally controlled oscillator (DCO) with a fast locking feature. To minimize the loop delay and thereby improve the jitter tolerance, the CDR design includes an additional proportional path that is realized by directly controlling the phase of the oscillator with the output signal of the phase detector. The design is all-digital, including digital filters that simplify the design. The CDR occupies an active area of 0.031 mm 2 , implemented in a 28-nm CMOS process. The receiver operates up to 12.5 Gb/s. The frequency locking time, measured as the time required for every 1-Gb/s change in the input data, is 320 ns. The power consumption is only 21.13 mW, corresponding to an energy efficiency of 2.11 pJ/bit.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2020.3005750