3-D Resistive Memory Arrays: From Intrinsic Switching Behaviors to Optimization Guidelines

3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A...

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Bibliographic Details
Published in:	IEEE transactions on electron devices Vol. 62; no. 10; pp. 3160 - 3167
Main Authors:	Haitong Li, Bin Gao, Chen, Hong-Yu Henry, Zhe Chen, Peng Huang, Rui Liu, Liang Zhao, Jiang, Zizhen Jane, Lifeng Liu, Xiaoyan Liu, Shimeng Yu, Jinfeng Kang, Yoshi Nishi, Wong, H.-S Philip
Format:	Journal Article
Language:	English
Published:	New York IEEE 01-10-2015 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	3-D array Computer architecture Electrical resistance measurement Microprocessors optimization Programming Random access memory Reliability Resistance resistive random access memory (RRAM) variability Voltage measurement resistive random access memory (RRAM) variability 3-D array optimization reliability
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Summary:	3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A systematic study on the intrinsic switching behaviors and optimization of 3-D RRAM arrays is performed, combining device measurements and 3-D array simulations. The dependence of programming voltage on array size, cell location and pulse parameters, statistical properties of operating 3-D RRAM arrays, and subthreshold disturbance on RRAM cells is experimentally investigated. Optimization guidelines for the performance and reliability of 3-D RRAM arrays from device level to architecture level are presented: 1) an optimized 1/n architecture for 100-kb 3-D RRAM arrays can improve write margin by 69.6% and reduce energy consumption by 75.6% compared with a conventional full-size array design; 2) a strategy of prioritizing storage location for reliable operation is presented; and 3) an optimal hopping barrier of oxygen ions is found to improve array immunity to disturbance.
ISSN:	0018-9383 1557-9646
DOI:	10.1109/TED.2015.2468602