Search Results - "Jeongsup Lee"

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  1. 1

    A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation by Lee, Jeongsup, Miyoshi, Satoru, Kawaminami, Masaru, Blaauw, David, Sylvester, Dennis, Zhang, Yiqun, Dong, Qing, Lim, Wootaek, Saligane, Mehdi, Kim, Yejoong, Jeong, Seokhyeon, Lim, Jongyup, Yasuda, Makoto

    Published in IEEE journal of solid-state circuits (01-01-2020)
    “…Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a…”
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    Journal Article
  2. 2

    Al-doped ZnO as a switching layer for transparent bipolar resistive switching memory by Yu, Hyeongwoo, Kim, Minho, Kim, Yoonsu, Lee, Jeongsup, Kim, Kyoung-Kook, Choi, Sang-Jun, Cho, Soohaeng

    Published in Electronic materials letters (01-03-2014)
    “…In this report, we employ an Al-doped ZnO (AZO) layer as a resistive switching layer for transparent resistive switching random access memory devices. An…”
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    Journal Article
  3. 3

    An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime Replica Calibration by Saligane, Mehdi, Jeongsup Lee, Qing Dong, Yasuda, Makoto, Kumeno, Kazuyuki, Ohno, Fumitaka, Miyoshi, Satoru, Kawaminami, Masaru, Blaauw, David, Sylvester, Dennis

    Published in 2018 IEEE Symposium on VLSI Circuits (01-06-2018)
    “…This work proposes a hybrid approach combining the benefits of in situ timing slack monitoring and tunable replica techniques while avoiding their drawbacks…”
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    Conference Proceeding
  4. 4

    An ultra-wide program, 122pJ/bit flash memory using charge recycling by Jeloka, Supreet, Jeongsup Lee, Ziyun Li, Jinal Shah, Qing Dong, Kaiyuan Yang, Sylvester, Dennis, Blaauw, David

    Published in 2017 Symposium on VLSI Circuits (01-06-2017)
    “…Embedded flash for low power sensing systems require very low write energy and peak power. This work proposes a 130nm, 1024×260 SONOS flash with an ultra-wide…”
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    Conference Proceeding
  5. 5

    Design Techniques of Integrated Power Management Circuits for Low Power Edge Devices by Xu, Li, Lee, Jeongsup, Saligane, Mehdi, Blaauw, David, Sylvester, Dennis

    “…Edge devices are essential elements for Internet of Things (1oT). To extend the battery life or achieve batteryless operation through energy harvesting, low…”
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    Conference Proceeding
  6. 6

    A 0.3-V to 1.8-3.3-V Leakage-Biased Synchronous Level Converter for ULP SoCs by Lee, Jeongsup, Saligane, Mehdi, Blaauw, David, Sylvester, Dennis

    Published in IEEE solid-state circuits letters (2020)
    “…This letter proposes a robust synchronous wide-range clocked level converter (LC) that converts subthreshold input signals to high I/O voltages for ultra-low…”
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    Journal Article
  7. 7

    A Fully Integrated, Automatically Generated DC-DC Converter Maintaining >75% Efficiency From 398 K Down to 23 K Across Wide Load Ranges in 12 nm FinFET by Li, Anhang, Lee, Jeongsup, Mukim, Prashansa, Hoskins, Brian D., Shrestha, Pragya, Wentzloff, David, Blaauw, David, Sylvester, Dennis, Saligane, Mehdi

    Published in IEEE solid-state circuits letters (01-01-2024)
    “…This paper presents a fully integrated recursive successive-approximation switched capacitor (RSC) DC-DC converter implemented using an automatic cell-based…”
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    Journal Article
  8. 8
  9. 9

    75% Efficiency From 398 K Down to 23 K Across Wide Load Ranges in 12-nm FinFET by Li, Anhang, Lee, Jeongsup, Mukim, Prashansa, Hoskins, Brian D, Shrestha, Pragya, Wentzloff, David, Blaauw, David, Sylvester, Dennis, Saligane, Mehdi

    Published in IEEE solid-state circuits letters (01-01-2024)
    “…75% efficiency across a vast range of output currents and temperatures. Our design targets voltage scaling for applications, such as cryo-computing,…”
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    Journal Article
  10. 10

    A Noise-Efficient Neural Recording Amplifier Using Discrete-Time Parametric Amplification by Jang, Taekwang, Lim, Jongyup, Choo, Kyojin, Nason, Samuel, Lee, Jeongsup, Oh, Sechang, Chestek, Cynthia, Sylvester, Dennis, Blaauw, David

    Published in IEEE solid-state circuits letters (01-11-2018)
    “…This letter proposes an instrumentation amplifier for neural recording applications whose measured noise efficiency factor (NEF) is 2.2. A discrete-time…”
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    Journal Article
  11. 11
  12. 12

    A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards by Yoon, Taehun, Lee, Joon-Yeong, Han, Kwangseok, Lee, Jeongsup, Lee, Sangeun, Kim, Taeho, Won, Hyosup, Park, Jinho, Bae, Hyeon-Min

    “…This paper presents the industry's first low-power 100-Gigabit Ethernet (GbE) multi-link gearbox (MLG) IC, which facilitates transport of independent 10-GbE…”
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    Conference Proceeding Journal Article
  13. 13

    A \muProcessor Layer for mm-Scale Die-Stacked Sensing Platforms Featuring Ultra-Low Power Sleep Mode at 125°C by Lee, Jeongsup, Kim, Yejoong, Cho, Minchang, Yasuda, Makoto, Miyoshi, Satoru, Kawaminami, Masaru, Blaauw, David, Sylvester, Dennis

    “…This paper presents an ultra-low power sleep mode \mu processor layer designed for use in mm-scale die-stacked wireless sensing platforms for high temperature…”
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    Conference Proceeding