Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and...

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Bibliographic Details
Published in:	2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS) pp. 1 - 4
Main Authors:	Dae Seok Byeon, Chi-Weon Yoon, Hyun-Kook Park, Yong-Kyu Lee, Hyo-Jin Kwon, Yeong-Taek Lee, Ki-Sung Kim, Yong-Yeon Joo, In-Gyu Baek, Young-Bae Kim, Jeong-Dal Choi, Kye-Hyun Kyung, Jeong-Hyuk Choi
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-10-2014
Subjects:	3D-Stack Capacitance Cross-point Emerging memory High density Multi-bit cell NAND Application ReRAM Resistive switching Scaling limit Surges Switches Write Disturbance
Online Access:	Get full text
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Summary:	In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.
ISBN:	9781479942039 1479942030
DOI:	10.1109/NVMTS.2014.7060837