Search Results - "Jeong, Sera"
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A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation
Published in IEEE journal of solid-state circuits (01-01-2022)“…The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires…”
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Journal Article -
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13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18-02-2024)“…The increase in GPU-based AI applications, cloud-based gaming, and video streaming services has driven the need for new a graphics memory that operates at…”
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Conference Proceeding -
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25.1 A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13-02-2021)“…The demand for high-performance graphics systems used for artificial intelligence continues to grow; this trend requires graphics systems to achieve ever…”
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Conference Proceeding