Search Results - "Jentzsch, Eyck"
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Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
Published in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (14-03-2022)“…We propose a novel cross-level verification approach for processor verification at the Register-Transfer Level (RTL). The foundation is a randomized…”
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2
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing
Published in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) (25-03-2024)“…This paper presents a demonstrator chip for an industrial audio event detection application developed as part of the Scale4Edge project. The project aims at…”
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3
The Scale4Edge RISC-V Ecosystem
Published in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (14-03-2022)“…This paper introduces the project Scale4Edge. The project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. We…”
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4
Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study
Published in 2020 Forum for Specification and Design Languages (FDL) (15-09-2020)“…Extensive processor verification at the Register-Transfer Level (RTL) is crucial to avoid bugs. Therefore, simulation-based approaches are prevalent but they…”
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Bits, Flips and RISCs
Published in 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (03-05-2023)“…Electronic systems can be submitted to hostile environments leading to bit-flips or stuck-at faults and, ultimately, a system malfunction or failure. In…”
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Multi-agent Software Tool for Management of Design Process in Microelectronics
Published in 2006 IEEE/WIC/ACM International Conference on Intelligent Agent Technology (18-12-2006)“…The paper presents a software tool to support the management of design process in microelectronics. It is developed as a multi-agent prototype intended for…”
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