Search Results - "Jenihhin, M."

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems by Jenihhin, M., Hamdioui, S., Reorda, M. Sonza, Krstic, M., Langendorfer, P., Sauer, C., Klotz, A., Huebner, M., Nolte, J., Vierhaus, H. T., Selimis, G., Alexandrescu, D., Taouil, M., Schrijen, G. J., Raik, J., Sterpone, L., Squillero, G., Dyka, Z.

“…The recent trends for nanoelectronic computing systems include machine-to-machine communication in the era of Internet-of-Things (IoT) and autonomous systems,…”
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Hybrid BIST time minimization for core-based systems with STUMPS architecture by Jervan, G., Eles, P., Peng, Z., Ubar, R., Jenihhin, M.

“…This paper presents a solution to the test tone minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a…”
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Test time minimization for hybrid BIST of core-based systems by Jervan, Eles, Peng, Ubar, Jenihhin

“…This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled,…”
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Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG by Palermo, N., Tihhomirov, V., Copetti, T. S., Jenihhin, M., Raik, J., Kostin, S., Gaudesi, M., Squillero, G., Sonza Reorda, M., Vargas, F., Bolzani Poehls, L.

“…One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It…”
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Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs by Pellerey, Francesco, Jenihhin, Maksim, Squillero, Giovanni, Raik, Jaan, Reorda, Matteo Sonza, Tihhomirov, Valentin, Ubar, Raimund

“…The time-dependent variation caused by Negative Bias Temperature Instability (NBTI) is agreed to be one of the main reliability concerns in integrated circuits…”
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Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning by Ahmadilivani, Mohammad Hasan, Mousavi, Seyedhamidreza, Raik, Jaan, Daneshtalab, Masoud, Jenihhin, Maksim

“…Convolutional Neural Networks (CNNs) have become integral in safety-critical applications, thus raising concerns about their fault tolerance. Conventional…”
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Enhancing Fault Resilience of QNNs by Selective Neuron Splitting by Ahmadilivani, Mohammad Hasan, Taheri, Mahdi, Raik, Jaan, Daneshtalab, Masoud, Jenihhin, Maksim

“…The superior performance of Deep Neural Networks (DNNs) has led to their application in various aspects of human life. Safety-critical applications are no…”
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Hybrid BIST optimization for core-based systems with test pattern broadcasting by Ubar, R., Jenihhin, M., Jervan, G., Zebo Peng

“…This paper introduces a technique for hybrid BIST time optimization for testing core-based systems that use test pattern broadcasting for both pseudorandom and…”
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AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators by Taheri, Mahdi, Cherezova, Natalia, Nazari, Samira, Rafiq, Ahsan, Azarpeyvand, Ali, Ghasempouri, Tara, Daneshtalab, Masoud, Raik, Jaan, Jenihhin, Maksim

“…Multiplication is the most resource-hungry operation in the neural network's processing elements. In this paper, we propose an architecture of a novel adaptive…”
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SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators by Taheri, Mahdi, Daneshtalab, Masoud, Raik, Jaan, Jenihhin, Maksim, Pappalardo, Salvatore, Jimenez, Paul, Deveautour, Bastien, Bosio, Alberto

“…Systolic array has emerged as a prominent archi-tecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency…”
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Electronics design and testing of the CMS Fast Beam Condition Monitor for HL-LHC by Shibin, K, Auzinger, G, Bakhshiansohi, H, Dabrowski, A, Dierlamm, A, Dragicevic, M, Gholami, A, Gomez, G, Guthoff, M, Haranko, M, Homna, A, Jenihhin, M, Kaplon, J, Karacheban, O, Korcsmáros, B, Lokhovitskiy, A, Loos, R, Mallows, S, Michel, J, Myronenko, V, Pásztor, G, Schwandt, J, Sedghi, M, Shevelev, A, Steinbrueck, G, Stickland, D, Wegrzyn, G. J

“…The high-luminosity upgrade of the LHC (HL-LHC) brings unprecedented requirements for precision bunch-by-bunch luminosity measurement and beam-induced…”
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DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators by Taheri, Mahdi, Riazati, Mohammad, Ahmadilivani, Mohammad Hasan, Jenihhin, Maksim, Daneshtalab, Masoud, Raik, Jaan, Sjodin, Mikael, Lisper, Bjorn

“…While the role of Deep Neural Networks (DNNs) in a wide range of safety-critical applications is expanding, emerging DNNs experience massive growth in terms of…”
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The CMS Fast Beam Condition Monitor for HL-LHC by Auzinger, G, Bakhshiansohi, H, Dabrowski, A, Delannoy, A. G, Dierlamm, A, Dragicevic, M, Gholami, A, Gomez, G, Guthoff, M, Haranko, M, Homna, A, Jenihhin, M, Kaplon, J, Karacheban, O, Korcsmáros, B, Liu, W. H, Lokhovitskiy, A, Loos, R, Mallows, S, Michel, J, Myronenko, V, Pásztor, G, Pari, M, Schwandt, J, Sedghi, M, Shevelev, A, Shibin, K, Steinbrueck, G, Stickland, D, Ujvari, B, Wegrzyn, G. J

“…The high-luminosity upgrade of the LHC brings unprecedented requirements for real-time and precision bunch-by-bunch online luminosity measurement and…”
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New categories of Safe Faults in a processor-based Embedded System by Gursoy, C., Jenihhin, M., Oyeniran, A. S., Piumatti, D., Raik, J., Reorda, M. Sonza, Ubar, R.

“…The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its…”
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New categories of Safe Faults in a processor-based Embedded System by Gursoy, C. C, Jenihhin, M, Oyeniran, A. S, Piumatti, D, Raik, J, Reorda, M. Sonza, Ubar, R

“…The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its…”
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Test Time Minimization for Hybrid BIST of Core-Based Systems by Jervan, Gert, Eles, Petru, Peng, Zebo, Ubar, Raimund, Jenihhin, Maksim

“…This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled,…”
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Software-Based Mitigation for Memory Address Decoder Aging by Kraak, D.H.P., Gursoy, C.C., Agbo, I.O., Taouil, M., Jenihhin, M., Raik, J., Hamdioui, S.

“…Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary…”
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Extensible open-source framework for translating RTL VHDL IP cores to SystemC by Syed, S. A., Jenihhin, M., Raik, J.

“…SystemC has gained wide acceptance in the design of VLSI SoCs. At the same time there exists a large number of legacy IP cores described in VHDL whose reuse…”
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TTBist: a DfT Tool for Enhancing Functional Test for SoC by Hermann, K., Raik, J., Jenihhin, M.

“…The paper presents a new tool called TTBist for DfT synthesis of IP cores in systems-on-a-chip. While scan-based approaches have been known for a long time,…”
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Combining dynamic slicing and mutation operators for ESL correction by Repinski, U., Hantson, H., Jenihhin, M., Raik, J., Ubar, R., Di Guglielmo, G., Pravadelli, G., Fummi, F.

“…Verification is increasingly becoming the bottleneck in designing digital systems. In fact, most of the verification cycle is not spent on detecting the…”
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