Search Results - "Jen-Chou Tseng"

ESD and Latchup Optimization of an Embedded-Floating-pMOS SCR-Incorporated BJT by Chih-Yao, Huang, Fu-Chien, Chiu, Chien-Min Ou, Chen, Quo-Ker, Yi-Jou, Huang, Jen-Chou Tseng

“…This paper develops optimization between electrostatic discharge (ESD) and latchup characteristics for a silicon-controlled rectifier (SCR)-incorporated…”
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Lateral Nonuniformity Effects of Border Traps on the Characteristics of Metal-Oxide-Semiconductor Field-Effect Transistors Subjected to High-Field Stresses by TSENG, Jen-Chou, HWU, Jenn-Gwo

“…The lateral nonuniformity (LNU) effects of border traps are studied by exploring both the high- and low-frequency characteristics in N-type channel…”
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Oxide-Trapped Charges Induced by Electrostatic Discharge Impulse Stress by Tseng, Jen-Chou, Hwu, Jenn-Gwo

“…The characteristics of oxide-trapped charges Q ot induced by electrostatic discharge high-field current impulse stress, i.e., transmission line pulsing (TLP),…”
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Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS by Chun-Yu Lin, Mei-Lian Fan, Ming-Dou Ker, Li-Wei Chu, Jen-Chou Tseng, Ming-Hsiang Song

“…To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit…”
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ESD protection design for wideband RF applications in 65-nm CMOS process by Li-Wei Chu, Chun-Yu Lin, Ming-Dou Ker, Ming-Hsiang Song, Jen-Chou Tseng, Chewn-Pu Jou, Ming-Hsien Tsai

“…All wireless communication products must meet the reliability specifications during mass production. To prevent from electrostatic discharge (ESD) damages, the…”
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Characterization of the electrostatic discharge induced interface traps in metal-oxide-semiconductor field-effect transistors by Jen-Chou Tseng, Jenn-Gwo Hwu

“…The interface trap's characteristics in silicon dioxide induced by electrostatic discharge current impulse were studied using the transmission line pulsing…”
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Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology by Li-Wei Chu, Chun-Yu Lin, Shiang-Yu Tsai, Ming-Dou Ker, Ming-Hsiang Song, Chewn-Pu Jou, Tse-Hua Lu, Jen-Chou Tseng, Ming-Hsien Tsai, Tsun-Lai Hsu, Ping-Fang Hung, Tzu-Heng Chang

“…Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided…”
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A 6.5kV ESD-protected low noise amplifier in 65-nm CMOS by Ming-Hsien Tsai, Fu-Lung Hsueh, Chewn-Pu Jou, Ming-Hsiang Song, Jen-Chou Tseng, Hsu, Shawn S H, Sean Chen

“…A new ESD topology is proposed for RF low-noise amplifier (LNA). By using the modified silicon-controlled rectifier (MSCR) in conjunction with a P + /N-well…”
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Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits by Jen-Chou Tseng, Yu-Lin Chen, Chung-Ti Hsu, Fu-Yi Tsai, Po-An Chen, Ming-Dou Ker

“…An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated cricuits. The latchup test resulted in damage to the output…”
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An on-chip combo clamp for surge and universal ESD protection in bulk FinFET technology by Ming-Fu Tsai, Jen-Chou Tseng, Chung-Yu Huang, Tzu-Heng Chang, Kuo-Ji Chen, Ming-Hsiang Song

“…A surge protection consisted of the ready-made ESD clamp transistors has been designed and characterized in FINFET technology. It can endure all the stresses…”
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Investigation and solution to the early failure of parasitic NPN triggered by the adjacent PNP ESD clamps by Ming-Fu Tsai, Jen-Chou Tseng, Kuo-Ji Chen, Ming-Hsiang Song

“…The mechanism of PNP-triggered parasitic NPN's early failure during ESD stress has been clarified for the first time. We proposed two solutions for the high…”
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A high latchup - Immune ESD protection SCR-incorporated BJT in deep submicron technology by Chih-Yao Huang, Fu-Chien Chiu, Ji-Fan Chi, Yi-Jou Huang, Quo-Ker Chen, Jen-Chou Tseng

“…An SCR-incorporated BJT for latchup and ESD optimization is developed in a 0.18μm-3.3V process. This device simply consists of a floating P + region in a…”
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ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology by Lin, Chun-Yu, Chu, Li-Wei, Tsai, Shiang-Yu, Ker, Ming-Dou, Song, Ming-Hsiang, Jou, Chewn-Pu, Lu, Tse-Hua, Tseng, Jen-Chou, Tsai, Ming-Hsien, Hsu, Tsun-Lai, Hung, Ping-Fang, Wei, Yu-Lin, Chang, Tzu-Heng

“…Nanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology…”
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ESD protection structure with inductor-triggered SCR for RF applications in 65-nm CMOS process by Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, Ming-Hsiang Song, Chewn-Pu Jou, Tse-Hua Lu, Jen-Chou Tseng, Ming-Hsien Tsai, Tsun-Lai Hsu, Ping-Fang Hung, Tzu-Heng Chang

“…To protect radio-frequency (RF) integrated circuits from electrostatic discharge (ESD) damages, silicon-controlled rectifier (SCR) devices have been used as…”
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An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS by Ming-Hsien Tsai, Hsu, S S H, Fu-Lung Hsueh, Chewn-Pu Jou, Tzu-Jin Yeh, Ming-Hsiang Song, Jen-Chou Tseng

“…This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of…”
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Design of ESD protection cell for dual-band RF applications in a 65-nm CMOS process by Li-Wei Chu, Chun-Yu Lin, Shiang-Yu Tsai, Ming-Dou Ker, Ming-Hsiang Song, Chewn-Pu Jou, Tse-Hua Lu, Jen-Chou Tseng, Ming-Hsien Tsai, Tsun-Lai Hsu, Ping-Fang Hung, Tzu-Heng Chang, Yu-Lin Wei

“…An ESD protection cell consisted of a diode, a silicon-controlled rectifier (SCR), a PMOS, and inductors was proposed for dual-band radio-frequency (RF) ESD…”
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An efficient full-chip ESD paths resistance value verification flow for large scale designs by Meng-Fan Wu, Chun-Chien Tsai, Jen-Chou Tseng, Chao, Roger, Ming-Hsiang Song, Yi-Kan Cheng

“…Commercial EDA tools are available to verify resistance values of ESD paths. However, since ESD paths relate to whole-chip power/ground (P/G) nets,…”
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High CDM resistant low-cap SCR for 0.9V advanced CMOS technology by Yu-Ti Su, Tzu-Heng Chang, Tsung-Che Tsai, Li-Wei Chu, Jen-Chou Tseng, Ming-Hsiang Song

“…A novel SCR is proposed using a scrambling structure with a Schottky junction. It has ultra low capacitance, high holding voltage and superb CDM performance…”
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60 GHz low noise amplifiers with 1 kV CDM protection in 40 nm LP CMOS by Raczkowski, K., Thijs, S., Jen-Chou Tseng, Tzu-Heng Chang, Ming-Hsiang Song, Linten, D., Nauwelaers, B., Wambacq, P.

“…This paper describes a set of miniature, three-stage 60 GHz LNAs designed in 40 nm LP CMOS. The designs prove effectiveness and ease of use of inductor-based…”
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High-k metal gate-bounded Silicon Controlled Rectifier for ESD protection by Chang, T., Hsu, Y., Tsai, T., Tseng, J., Lee, J., Song, M.

“…An ultra-low trigger gate-bounded SCR using a high-k metal gate process is proposed, which has a superb immunity to protect thin oxide against CDM-like…”
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