Search Results - "Jaysankar, M."

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node by Gupta, A., Mertens, H., Tao, Z., Demuynck, S., Bommels, J., Arutchelvan, G., Devriendt, K., Pedreira, O. Varela, Ritzenthaler, R., Wang, S., Radisic, D., Kenis, K., Teugels, L., Sebaai, F., Lorant, C., Jourdan, N., Chan, B. T., Zahedmanesh, H., Subramanian, S., Schleicher, F., Hopf, T., Peter, A., Rassoul, N., Debruyn, H., Demonie, I., Siew, Y., Chiarella, T., Briggs, B., Zhou, D., Rosseel, E., De Keersgieter, A., Capogreco, E., Litta, E. Dentoni, Boccardi, G., Baudot, S., Mannaert, G., Bontemps, N., Sepulveda, A., Mertens, S., Kim, M. S., Dupuy, E., Vandersmissen, K., Paolillo, S., Yakimets, D., Chehab, B., Favia, P., Drijbooms, C., Cousserier, J., Jaysankar, M., Lazzarino, F., Morin, P., Sanchez, E., Mitard, J., Wilson, C., Holsteyns, F., Tokei, Z., Horiguchi, N.

“…Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of…”
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Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations by Vega-Gonzalez, V., Montero, D., Versluijs, J., Pedreira, O. Varela, Jourdan, N., Puliyalil, H., Chehab, B., Peissker, T., Haider, A., Batuk, D., Martinez, G. T., Geypen, J., Le, Q. T., Bazzazian, N., Heylen, N., van der Veen, M., El-Mekki, Z., Webers, T., Vats, H., Rynders, L., Cupak, M., Uk-Lee, J., Drissi, Y., Halipre, L., Gillijns, W., Charley, A.-L., Verdonck, P., Witters, T., Gompel, S. V., Kimura, Y., Ciofi, I., De Wachter, B., Swerts, J., Grieten, E., Ercken, M., Kim, R., Croes, K., Leray, P., Jaysankar, M., Nagesh, N., Ramakers, L., Murdoch, G., Park, S., Tokei, Z., Dentoni-Litta, E., Horiguchi, N.

“…The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison…”
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Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium by Vega-Gonzalez, V., Puliyalil, H., Versluijs, J., Lesniewska, A., Varela-Pereira, O., Baert, R., Paolillo, S., Decoster, S., Schleicher, F., Montero, D., Bekaert, J., Kesters, E., Le, Q. T., Lorant, C., Teugels, L., Heylen, N., Jourdan, N., El-Mekki, Z., van der Veen, M., Ciofi, I., Briggs, B., Heijlen, J., Dupas, L., De-Wachter, B., Vancoille, E., Webers, T., Vats, H., Rynders, L., Cupak, M., Uk-Lee, J., Drissi, Y., Halipre, L., Charley, A.-L., Verdonck, P., Witters, T., Gompel, S. V., Kimura, Y., Demonie, I., Lazzarino, F., Ercken, M, Kim, R., Trivkovic, D., Croes, K., Leray, P., Jaysankar, M., Wilson, C., Muroch, G., Tokei, Z.

“…The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated…”
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