Search Results - "Jaussi, J.E."

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture by Casper, B., Martin, A., Jaussi, J.E., Kennedy, J., Mooney, R.

“…A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-/spl mu/m CMOS. This equalized transceiver has been optimized for small area (329…”
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8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew by Jaussi, J.E., Balamurugan, G., Johnson, D.R., Casper, B., Martin, A., Kennedy, J., Shanbhag, N., Mooney, R.

“…A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-/spl mu/m bulk CMOS technology. The transceiver is…”
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A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS by Balamurugan, Ganesh, Kennedy, Joseph, Banerjee, Gaurab, Jaussi, James E., Mansuri, Mozhgan, O'Mahony, Frank, Casper, Bryan, Mooney, Randy

“…We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power…”
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Modeling and Analysis of High-Speed I/O Links by Balamurugan, G., Casper, B., Jaussi, J.E., Mansuri, M., O'Mahony, F., Kennedy, J.

“…Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy…”
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High-Speed Flex-Circuit Chip-to-Chip Interconnects by Braunisch, H., Jaussi, J.E., Mix, J.A., Trobough, M.B., Horine, B.D., Prokofiev, V., Daoqiang Lu, Baskaran, R., Meier, P.C.H., Dong-Ho Han, Mallory, K.E., Leddige, M.W.

“…High-speed chip-to-chip interconnect utilizing flex-circuit technology is investigated for extending the lifetime of copper-based system-level channels. Proper…”
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Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver by Shekhar, S., Balamurugan, G., Allstot, D.J., Mansuri, M., Jaussi, J.E., Mooney, R., Kennedy, J., Casper, B., O'Mahony, F.

“…A general model for injection-locked LC oscillators (LC-ILOs) is presented that is valid for any tank quality factor and injection strength. Important…”
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Strong Injection Locking in Low-[Formula Omitted] LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver by Shekhar, S, Balamurugan, G, Allstot, D.J, Mansuri, M, Jaussi, J.E, Mooney, R, Kennedy, J, Casper, B, O'Mahony, F

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Future Microprocessor Interfaces: Analysis, Design and Optimization by Casper, B., Balamurugan, G., Jaussi, J.E., Kennedy, J., Mansuri, M.

“…High-aggregate bandwidth interfaces with minimized power, silicon area, cost and complexity will be essential to the viability of future microprocessor…”
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A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS by Balamurugan, G., O'Mahony, F., Mansuri, M., Jaussi, J.E., Kennedy, J.T., Casper, B.

“…A reconfigurable transceiver capable of adapting its signaling mode to the I/O channel is implemented in 45nm CMOS. When configured for single-ended 2/3/4-PAM,…”
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A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS by O'Mahony, F., Kennedy, J., Jaussi, J.E., Balamurugan, G., Mansuri, M., Roberts, C., Shekhar, S., Mooney, R., Casper, B.

“…A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. A dense interconnect topology allows clocking to be shared across…”
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An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew by Jaussi, J.E., Balamurugan, G., Johnson, D.R., Casper, B.K., Martin, A., Kennedy, J.T., Shanbhag, N., Mooney, R.

“…An 8Gb/s binary source-synchronous I/O link with adaptive receiver-equalization, offset cancellation and clock deskew is implemented in 0.13/spl mu/m CMOS. The…”
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The future of electrical I/O for microprocessors by O'Mahony, F., Balamurugan, G., Jaussi, J.E., Kennedy, J., Mansuri, M., Shekhar, S., Casper, B.

“…High-speed CMOS microprocessor I/O has scaled aggressively over the past decade in terms of power and performance largely due to advances in equalization and…”
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A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS by Balamurugan, G., Kennedy, J., Banerjee, G., Jaussi, J.E., Mansuri, M., O'Mahony, F., Casper, B., Mooney, R.

“…This paper presents a scalable low power I/O transceiver in 65nm CMOS capable of 5-15Gbps operation over 8" FR4 with power efficiencies between 3-5mW/Gbps…”
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High-Speed Flex Chip-to-Chip Interconnect by Braunisch, H., Jaussi, J.E., Mix, J.A.

“…Signaling rates up to 20 Gb/s on a flex-circuit chip-to-chip interconnect are reported in active testing based on 90-nm CMOS circuits. The characterization of…”
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A Low-Jitter PLL and Repeaterless Clock Distribution Network for a 20Gb/s Link by O'Mahony, F., Mansuri, M., Casper, B., Jaussi, J.E., Mooney, R.

“…A 10GHz clock generation and distribution network for an 8-channel 20Gb/s/channel data transmitter is demonstrated in a 90nm 1.2V CMOS process. Jitter due to…”
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In-situ jitter tolerance measurement technique for Serial I/O by Jaussi, J.E., Balamurugan, G., Kennedy, J., O'Mahony, F., Mansuri, M., Mooney, R., Casper, B., Un-Ku Moon

“…A 10.2-12.5 Gb/s CDR incorporating an on-die jitter modulation circuit that enables in-situ jitter tolerance testing is demonstrated in 65 nm CMOS. Sinusoidal…”
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Flex-circuit chip-to-chip interconnects by Braunisch, H., Jaussi, J.E., Mix, J.A., Trobough, M.B., Horine, B.D., Prokofiev, V., Daoqiang Lu, Baskaran, R., Meier, P.C.H., Dong-Ho Han, Mallory, K.E., Leddige, M.W.

“…High-speed chip-to-chip interconnect utilizing flex-circuit technology is investigated for extending the lifetime of copper-based system-level channels. Proper…”
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