Search Results - "Jang, S.L"
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1
Simulated soil organic carbon stocks in northern China’s cropland under different climate change scenarios
Published in Soil & tillage research (01-09-2021)“…•The study predicated the influence of future climate change scenarios on SOC stock in oasis land.•DNDC model can be applied in Chinese northern arid basin by…”
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2
Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure
Published in Thin solid films (03-05-2010)“…The formation of a poly-Si thin-film transistor (TFT) device with a tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate…”
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3
Study of ultra-shallow p +n junctions formed by excimer laser annealing
Published in Materials chemistry and physics (01-09-2010)“…Excellent ultra-shallow p +n junctions have been formed by thermally treating the BF 2 +-implanted Si samples by excimer laser annealing (ELA) at 300–400 mJ cm…”
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4
Experimental evaluation of hot electron reliability on differential Clapp-VCO
Published in Microelectronics and reliability (01-02-2013)“…This paper studies the hot-carrier stressed property of a series-tuned all-n core voltage controlled oscillator (VCO). A differential Clapp-VCO has been…”
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5
Formation of Mo gate electrode with adjustable work function on thin Ta 2O 5 high- k dielectric films
Published in Solid-state electronics (2006)“…Formation of Mo gate electrode with adjustable work function on thin Ta 2O 5 high- k dielectric films at low-temperature processing of 600 °C has been studied…”
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6
Submicron-meter polycrystalline-SiGe thin-film transistors with tunneling field-effect-transistor structure
Published in Solid-state electronics (01-12-2010)“…Submicron-meter polycrystalline-SiGe thin-film transistor (TFT) device with tunneling field-effect-transistor (TFET) structure has been studied. With scaling…”
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7
Study of polycrystalline-Si thin-film transistors with different channel layer thickness at low bias voltage
Published in Microelectronic engineering (01-10-2010)“…A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead…”
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8
The formation of polycrystalline-Si thin-film transistors by using large-angle-tilt-implantation of dopant through gate sidewall spacer
Published in Solid-state electronics (01-09-2009)“…Formation of poly-Si thin-film transistor (TFT) by large-angle-tilt-implantation of dopant through gate sidewall spacer (LATITS) has been proposed. By this…”
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9
Formation of 30-V power DMOSFET’s by implementing p-counter-doped region within n-type drift layer
Published in Solid-state electronics (01-07-2010)“…Formation of 30-V power DMOSFET device by implementing p-counter-doped region within n-drift layer has been proposed. The implementation of p-counter-doped…”
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10
Formation of sub-micrometer polycrystalline-SiGe thin-film transistors by using a thinned channel layer
Published in Solid-state electronics (01-03-2010)“…A sub-micron poly-SiGe TFT device, operating at a drain bias of 1.5 V, is proposed by using a thinned channel layer. A thinner channel layer may lead to better…”
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11
Formation of Mo gate electrode with adjustable work function on thin Ta2O5 high-k dielectric films
Published in Solid-state electronics (01-02-2006)Get full text
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12
Fabrication of trench-gate power MOSFETs by using a dual doped body region
Published in Solid-state electronics (01-07-2004)“…Fabrication of trench-gate power MOSFETs by using a dual doped body region has been proposed to further improve the device performance. For the usual scheme…”
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13
A design consideration of channel doping profile for sub-0.12 μm partially depleted SOI n-MOSFET's
Published in Solid-state electronics (01-08-2002)“…A device scheme for designing sub-0.12 μm partially depleted silicon-on-insulator (SOI) n-MOSFET's has been examined with respect to the channel dopant…”
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14
An analytical high frequency noise model for hot-carrier stressed MOSFETs
Published in Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004 (2004)“…This paper proposes a hot-carrier stressed high frequency noise model for MOSFETs. By analytical method, a new fresh and post-stress high-frequency MOSFET…”
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