Search Results - "Jancke, R."

NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling by Giering, K.-U., Puschkarsky, K., Reisinger, H., Rzepa, G., Rott, G., Vollertsen, R., Grasser, T., Jancke, R.

“…We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages…”
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Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh En§ironments by Warmuth, J., Giering, K.-U., Lange, A., Clausner, A., Schlipf, S., Kurz, G., Otto, M., Paul, J., Jancke, R., Aal, A., Gall, M., Zschech, E.

“…On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress…”
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Analog-circuit NBTI degradation and time-dependent NBTI variability: An efficient physics-based compact model by Giering, K.-U, Rott, G., Rzepa, G., Reisinger, H., Puppala, A. K., Reich, T., Gustin, W., Grasser, T., Jancke, R.

“…We experimentally and theoretically investigate the NBTI degradation of pMOS devices due to analog stress voltages and thus go beyond existing NBTI studies for…”
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Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology by Lorenz, Jürgen K., Bar, E., Clees, T., Jancke, R., Salzig, C. P. J., Selberherr, S.

“…Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design…”
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Analysis of 28 nm SRAM cell stability under mechanical load applied by nanoindentation by Clausner, A., Schlipf, S., Kurz, G., Otto, M., Paul, J., Giering, K.-U., Warmuth, J., Lange, A., Jancke, R., Aal, A., Rosenkranz, R., Gall, M., Zschech, E.

“…28 nm high-k metal gate CMOS SRAM circuits were subjected to controlled mechanical load by nanoindentation. A thinning procedure down to about 35 μm of…”
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Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Results by Lorenz, J. K., Bar, E., Clees, T., Evanschitzky, P., Jancke, R., Kampen, C., Paschen, U., Salzig, C. P. J., Selberherr, S.

“…Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design…”
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Generator based approach for analog circuit and layout design and optimization by Graupner, A, Jancke, R, Wittmann, R

“…Layout generation remains a critical bottleneck in analog circuit design. It is especially distracting when re-using an existing design for a similar…”
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A general approach for multivariate statistical MOSFET compact modeling preserving correlations by Lange, A., Sohrmann, C., Jancke, R., Haase, J., Binjie Cheng, Kovac, U., Asenov, A.

“…As feature sizes shrink, random fluctuations gain importance in semiconductor manufacturing and integrated circuit design. Therefore, statistical device…”
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Supporting analog synthesis by abstracting circuit behavior using a modeling methodology by Jancke, R., Schwarz, P.

“…For analog and mixed-signal circuit design a modeling methodology is needed which is well suited to the requirements of a structured synthesis flow. It ensures…”
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System-level time-domain behavioral baseband modeling of RF blocks for mixed-signal simulation by Harasymiv, I., Jancke, R.

“…This article presents a short survey of existing baseband (BB) signal flow models of linear and nonlinear RF blocks for system-level (SL) time domain (TD)…”
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Simulation of electro-thermal interaction by Jancke, R, Wilde, A, Martin, R, Reitz, S, Schneider, P

“…There is an increasing demand for simulation strategies for electro-thermal analysis of electronic systems. In this study cases are investigated, where self…”
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Das Wesen der Ironie. Eine Strukturanalyse ihrer Erscheinungsformen by Kluver, Heinrich, Jancke, R.

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