Search Results - "Janai, M."
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1
Data retention, endurance and acceleration factors of NROM devices
Published in 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual (2003)“…Reliability studies of Saifun NROM devices are presented. Data retention characteristics vs time, temperature and cycling level are explained based on a charge…”
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Conference Proceeding -
2
The kinetics of degradation of data retention of post-cycled NROM non-volatile memory products
Published in 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual (2005)“…The kinetics of degradation of the threshold voltage of post-cycled NROM products is investigated. The root cause of the threshold voltage drift is attributed…”
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3
Threshold Voltage Fluctuations in Localized Charge-Trapping Nonvolatile Memory Devices
Published in IEEE transactions on electron devices (01-03-2012)“…Threshold voltage fluctuations are studied in localized charge-trapping nonvolatile memory devices. Intensive program/erase cycling followed by…”
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4
Charge Gain, NBTI, and Random Telegraph Noise in EEPROM Flash Memory Devices
Published in IEEE electron device letters (01-09-2010)“…Different charge-gain (CG) processes are reported in EEPROM nonvolatile Flash memory devices. The process originally characterized in nitride-trapping devices…”
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5
Charge gain, NBTI recovery and random telegraph noise in localized-trapping NVM devices
Published in 2011 International Reliability Physics Symposium (01-04-2011)“…Three different physical reliability processes - charge gain (CG) in EEPROM nonvolatile memory devices, the recovery of negative bias temperature instability…”
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6
Plasma polymer films for 532 nm laser micromachining
Published in Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures (01-11-1998)“…Laser micromachining with a frequency doubled Nd:YAG laser (532 nm) can replace more complex microlithographic processes for rapid turnaround in the…”
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7
Relaxation of localized charge in trapping-based nonvolatile memory devices
Published in 2008 IEEE International Reliability Physics Symposium (01-04-2008)“…Relaxation dynamics of trapped holes and trapped electrons in the ONO layer of NROM devices is studied. Hole relaxation is eight orders of magnitude faster…”
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8
Optical absorption and photoluminescence of glow-discharge amorphous Si: F films
Published in Physical review. B, Condensed matter (15-05-1985)Get full text
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Properties of fluorinated glow-discharge amorphous silicon
Published in Physical review. B, Condensed matter (15-04-1985)Get full text
Journal Article -
10
Data retention reliability model of NROM nonvolatile memory products
Published in IEEE transactions on device and materials reliability (01-09-2004)“…Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a…”
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Magazine Article -
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The two-bit NROM reliability
Published in IEEE transactions on device and materials reliability (01-09-2004)“…Saifun NROM/spl trade/ is a novel localized charge-trapping-based nonvolatile memory technology that employs inherent two-bits-per-cell operation. NROM…”
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Magazine Article -
12
Photodissolution of Silver in Amorphous As 2 S 3 Films
Published in Physical review letters (01-07-1982)Get full text
Journal Article -
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Photodissolution of Silver in Amorphous As 2 S 3 Films
Published in Physical review letters (01-09-1981)Get full text
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14
Re-engineering ASIC design with LPGAs
Published in Proceedings of Eighth International Application Specific Integrated Circuits Conference (1995)“…The availability of Laser Programmable Gate-Arrays (LPGAs) of over 100k gates which can be economically produced within a few hours simplifies considerably the…”
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15
Highly scalable and manufacturable heterogeneous charge trap NAND technology
Published in 2013 5th IEEE International Memory Workshop (01-05-2013)“…For the first time, we will present production-ready heterogeneous charge trap NAND technology based on Silicon Rich Nitride. The competitive product…”
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16
4-bit per cell NROM reliability
Published in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest (2005)“…The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required…”
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Conference Proceeding