Search Results - "Janai, M."

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  1. 1

    Data retention, endurance and acceleration factors of NROM devices by Janai, M.

    “…Reliability studies of Saifun NROM devices are presented. Data retention characteristics vs time, temperature and cycling level are explained based on a charge…”
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    Conference Proceeding
  2. 2

    The kinetics of degradation of data retention of post-cycled NROM non-volatile memory products by Janai, M., Eitan, B.

    “…The kinetics of degradation of the threshold voltage of post-cycled NROM products is investigated. The root cause of the threshold voltage drift is attributed…”
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    Conference Proceeding
  3. 3

    Threshold Voltage Fluctuations in Localized Charge-Trapping Nonvolatile Memory Devices by Janai, M., Meng Chuan Lee

    Published in IEEE transactions on electron devices (01-03-2012)
    “…Threshold voltage fluctuations are studied in localized charge-trapping nonvolatile memory devices. Intensive program/erase cycling followed by…”
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    Journal Article
  4. 4

    Charge Gain, NBTI, and Random Telegraph Noise in EEPROM Flash Memory Devices by Janai, M, Bloom, I

    Published in IEEE electron device letters (01-09-2010)
    “…Different charge-gain (CG) processes are reported in EEPROM nonvolatile Flash memory devices. The process originally characterized in nitride-trapping devices…”
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    Journal Article
  5. 5

    Charge gain, NBTI recovery and random telegraph noise in localized-trapping NVM devices by Janai, M, Bloom, I, Shur, Y

    “…Three different physical reliability processes - charge gain (CG) in EEPROM nonvolatile memory devices, the recovery of negative bias temperature instability…”
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    Conference Proceeding
  6. 6

    Plasma polymer films for 532 nm laser micromachining by Silverstein, M. S., Visoly, I., Kesler, O., Janai, M., Cassuto, Y.

    “…Laser micromachining with a frequency doubled Nd:YAG laser (532 nm) can replace more complex microlithographic processes for rapid turnaround in the…”
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    Journal Article
  7. 7

    Relaxation of localized charge in trapping-based nonvolatile memory devices by Janai, M., Shappir, A., Bloom, I., Eitan, B.

    “…Relaxation dynamics of trapped holes and trapped electrons in the ONO layer of NROM devices is studied. Hole relaxation is eight orders of magnitude faster…”
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    Conference Proceeding
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    Data retention reliability model of NROM nonvolatile memory products by Janai, M., Eitan, B., Shappir, A., Lusky, E., Bloom, I., Cohen, G.

    “…Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a…”
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    Magazine Article
  11. 11

    The two-bit NROM reliability by Shappir, A., Lusky, E., Cohen, G., Bloom, I., Janai, M., Eitan, B.

    “…Saifun NROM/spl trade/ is a novel localized charge-trapping-based nonvolatile memory technology that employs inherent two-bits-per-cell operation. NROM…”
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    Magazine Article
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    Re-engineering ASIC design with LPGAs by Janai, M.

    “…The availability of Laser Programmable Gate-Arrays (LPGAs) of over 100k gates which can be economically produced within a few hours simplifies considerably the…”
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    Conference Proceeding
  15. 15

    Highly scalable and manufacturable heterogeneous charge trap NAND technology by Haddad, S., Fang, S., Chang, K., Shetty, S., Chen, C., Kim, U., Fang, T., Ortiz, S., Thurgate, T., Ramsbey, M., Kang, I., Janai, M., Neo, J., Singh, P. K., Nagatani, G., Samqui, A., Sugino, R., Hui, A., Tsai, F., Bell, S., Matsumoto, D., Gabriel, C., Sun, Y., Pak, J., Tehrani, S.

    “…For the first time, we will present production-ready heterogeneous charge trap NAND technology based on Silicon Rich Nitride. The competitive product…”
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    Conference Proceeding
  16. 16

    4-bit per cell NROM reliability by Eitan, B., Cohen, G., Shappir, A., Eli Lusky, Givant, A., Janai, M., Bloom, I., Polansky, Y., Dadashev, O., Lavan, A., Sahar, R., Maayan, E.

    “…The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required…”
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    Conference Proceeding