Search Results - "Jallepalli, S."

Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers by Chindalore, G., Hareland, S.A., Jallepalli, S.A., Tasch, A.F., Maziar, C.M., Chia, V.K.F., Smith, S.

“…The authors report for the first time, accurately extracted experimental data for the threshold voltage shift (/spl Delta/V T ) due to quantum mechanical (QM)…”
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Electron and hole quantization and their impact on deep submicron silicon p- and n-MOSFET characteristics by Jallepalli, S., Bude, J., Shih, W.-K., Pinto, M.R., Maziar, C.M., Tasch, A.F.

“…A first-principles approach to inversion layer quantization, valid for arbitrarily complex band structures, has been developed. This has allowed, for the first…”
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A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETs by Hareland, S.A., Krishnamurthy, S., Jallepalli, S., Choh-Fei Yeap, Hasnat, K., Tasch, A.F., Maziar, C.M.

“…Successful scaling of MOS device feature size requires thinner gate oxides and higher levels of channel doping in order to simultaneously satisfy the need for…”
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Computationally efficient models for quantization effects in MOS electron and hole accumulation layers by Hareland, S.A., Manassian, M., Shih, W.-K., Jallepalli, S., Wang, H., Chindalore, G.L., Tasch, Al.F., Maziar, C.M.

“…In this paper, models appropriate for device simulators are developed which account for the quantum mechanical nature of accumulated regions. Accumulation…”
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A pseudo-lucky electron model for simulation of electron gate current in submicron NMOSFET's by Hasnat, K., Yeap, C.-F., Jallepalli, S., Shih, W.-K., Hareland, S.A., Agostinelli, V.M., Tasch, A.F., Maziar, C.M.

“…An energy parameterized pseudo-lucky electron model for simulation of gate current in submicron MOSFET's is presented in this paper. The model uses…”
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Thermionic emission model of electron gate current in submicron NMOSFETs by Hasnat, K., Choh-Fei Yeap, Jallepalli, S., Hareland, S.A., Shih, W.-K., Agostinelli, V.M., Tasch, A.F., Maziar, C.M.

“…A thermionic emission model based on a non-Maxwellian electron energy distribution function for the electron gate current in NMOSFET's is described. The model…”
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A physically-based model for quantization effects in hole inversion layers by Hareland, S.A., Jallepalli, S., Wei-Kai Shih, Haihong Wang, Chindalore, G.L., Tasch, A.F., Maziar, C.M.

“…As MOS devices have been successfully scaled to smaller feature sizes, thinner gate oxides and higher levels of channel doping have been used in order to…”
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An experimental study of the effect of quantization on the effective electrical oxide thickness in MOS electron and hole accumulation layers in heavily doped Si by Chindalore, G., Shih, W.-K., Jallepalli, S., Hareland, S.A., Tasch, A.F., Maziar, C.M.

“…This work presents for the first time experimental results for the extraction of the increase in the effective electrical oxide thickness (/spl Delta/t/sub…”
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Effects of quantization on the electrical characteristics of deep submicron p- and n-MOSFETs by Jallepalli, S, Bude, J, Shih, W K, Pinto, M R, Maziar, C M, Tasch, A F

“…A first-principles approach to inversion layer quantization for arbitrarily complex band structures has been developed that has allowed, for the first time,…”
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A simple model for quantum mechanical effects in hole inversion layers in silicon PMOS devices by Hareland, S.A., Jallepalli, S., Chindalore, G., Shih, W.-K., Tasch, A.F., Maziur, C.M.

“…The effects of quantization of the inversion layer of MOSFET devices is an area of increasing importance as technology is aggressively scaled below 0.25 /spl…”
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CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET) by Mathew, L., Du, Y., Thean, A.V.-Y., Sadd, M., Vandooren, A., Parker, C., Stephens, T., Mora, R., Rai, R., Zavala, M., Sing, D., Kalpat, S., Hughes, J., Shimer, R., Jallepalli, S., Workman, G., Zhang, W., Fossum, J.G., White, B.E., Nguyen, B.-Y., Mogab, J.

“…Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to…”
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An accurate preprocessor for Monte Carlo study of electron transport in inversion layers of silicon nMOSFETs by Wei-Kai Shih, Hareland, S., Jallepalli, S., Maziar, C.M., Tasch, A.F.

“…Summary form only given. For a typical device simulation one cannot ignore the presence of nonuniformity in realistic MOSFET inversion layers. In this case,…”
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Modeling gate leakage current in nMOS structures due to tunneling through an ultra-thin oxide by Shih, Wei-Kai, Wang, Everett X., Jallepalli, Srinivas, Leon, Francisco, Maziar, Christine M., Tasch, Al F.

“…For the first time, the tunneling current in silicon nMOS structures with ultra-thin gate oxides has been studied both by numerically solving Schrödinger's…”
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Test structure and methodology for experimental extraction of threshold voltage shifts due to quantum mechanical effects in MOS inversion layers by Chindalore, G., Hareland, S., Jallepalli, S., Fasch, A.F., Maziar, C.M., Chia, V.K.F., Smith, S.

“…This paper reports the test structure and methodology that has been developed to experimentally extract the threshold voltage shifts </spl Delta/V/sub T/> due…”
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A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETs by Hareland, S.A., Krishnamurthy, S., Jallepalli, S., Yeap, C.-F., Hasnat, K., Tasch, A.F., Maziar, C.M.

“…This paper describes the development and implementation of a computationally efficient and accurate model for the prediction of quantum mechanical (QM) effects…”
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Understanding the differences in the effective-field dependence of electron and hole inversion layer mobilities by Jallepalli, S., Shih, W.-K., Bude, J.D., Pinto, M.R., Maziar, C.M., Tasch, A.F.

“…For the first time, results from a first-principles study of carrier quantization are coupled to realistic Monte Carlo (MC) simulations to investigate MOS…”
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Analysis of quantization effects in silicon (100) inversion layers using a Monte Carlo tool by Shih, W.-K., Jallepalli, S., Yeap, C.-F., Rashed, M., Maziar, C.M., Tasch, A.F.

“…The continued reduction of gate oxide thicknesses and increase of channel doping has created an important need for careful treatment of inversion layer…”
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Device simulations for low voltage/low power silicon CMOS device design by Jallepalli, Srinivas, Rashed, Mahbub, Zdebel, Peter

“…Device simulations are becoming an increasingly attractive alternative to traditional, experiment-based technology development. This is due to the…”
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Impact of channel doping and Ar implant on device characteristics of partially depleted SOI MOSFETs by Xu, X., Widenhofer, R., Rashed, M., Jallepalli, S., Thorn, J., Mendicino, M., Candelaria, J.

“…It is known that partially depleted (PD) SOI MOSFETs have floating body (FB) effects which degrade device performance. Previously, an argon (Ar) implant…”
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Efficacy of Ar in reducing the kink effect on floating-body NFD/SOI CMOS by Chang, D., Veeraraghavan, S., Mendicino, M., Rashed, M., Connelly, D., Jallepalli, S., Candelaria, J.

“…Despite recent reports of high speed nonfully-depleted (NFD) silicon-on-insulator (SOI) CMOS processes (Assaderaghi et al. 1997), there are growing concerns…”
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