Search Results - "Jagadesh Kumar, M."

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor by Saurabh, S, Kumar, M J

“…In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current,…”
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Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain by Abdi, Dawit B., Kumar, M. Jagadesh

“…In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel…”
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Dielectric-Modulated Impact-Ionization MOS Transistor as a Label-Free Biosensor by Kannan, N., Kumar, M. Jagadesh

“…In this letter, we propose a dielectric-modulated impact-ionization MOS (DIMOS) transistor-based sensor for application in label-free detection of…”
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Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer by Nadda, Kanika, Kumar, M. Jagadesh

“…A self-aligned vertical Bipolar Charge Plasma Transistor (V-BCPT) with a buried metal layer between undoped silicon and buried oxide of the…”
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Impact of gate leakage considerations in tunnel field effect transistor design by Chaturvedi, Poornendu, Kumar, M. Jagadesh

“…In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-κ gate dielectric) on the subthreshold…”
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The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs by Jagadesh Kumar, M., Siva, M.

“…The ground plane (GP) concept is one of the techniques used to reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs and is effective only when…”
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Compact Analytical Model of Dual Material Gate Tunneling Field-Effect Transistor Using Interband Tunneling and Channel Transport by Vishnoi, Rajat, Kumar, M. Jagadesh

“…In this paper, we have developed a 2-D analytical model for surface potential and drain current for a long channel dual material gate (DMG)…”
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Doping-Less Tunnel Field Effect Transistor: Design and Investigation by Kumar, M. Jagadesh, Janardhanan, Sindhu

“…Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge…”
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Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET by Vishnoi, Rajat, Kumar, M. Jagadesh

“…In this paper, we propose a 2-D analytical model for surface potential and drain current for a long channel p-type gate-all-around nanowire tunneling field…”
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A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor by Agrawal, Ashutosh Kumar, Koutilya, P. N. V. R., Jagadesh Kumar, M.

“…In this paper, we have developed a pseudo two-dimensional (2-D) analytical model for the surface potential of a dual-material double-gate junctionless…”
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Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device by Kumar, M. J., Nadda, K.

“…A distinctive approach for forming a lateral bipolar charge-plasma transistor (BCPT) is explored using 2-D simulations. Different metal work-function…”
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Schottky Collector Bipolar Transistor Without Impurity Doped Emitter and Base: Design and Performance by Nadda, Kanika, Kumar, M. Jagadesh

“…In this brief, we report an alternative approach of implementing a Schottky collector bipolar transistor without doping the ultrathin silicon-on-insulator…”
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Recessed source concept in nanoscale vertical surrounding gate (VSG) MOSFETs for controlling short-channel effects by Subrahmanyam, B., Jagadesh Kumar, M.

“…In the recent past, vertical surrounding gate (VSG) MOSFETs have gained importance since defining their nanoscale channel length no longer depends on…”
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Investigation of a new modified source/drain for diminished self-heating effects in nanoscale MOSFETs using computer simulation by Jagadesh Kumar, M., Orouji, Ali A.

“…In this paper, we demonstrate that by introducing a buried oxide in a bulk MOSFET only under the source and drain regions, i.e., using an oxygen implanted…”
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Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region by Agarwal, P., Saraswat, G., Kumar, M.J.

“…In this paper, by solving the 1-D Poisson equation using appropriate boundary conditions, we report a closed-form surface potential solution for all the three…”
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Analytical drain current model for nanoscale strained-Si SiGe MOSFETs by Batwani, Himanshu, Gaur, Mayank, Jagadesh Kumar, M.

“…Purpose - The purpose of this paper is to present an analytical drain current model for output characteristics of strained-Si SiGe bulk MOSFET.Design…”
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A New Buried-Oxide-In-Drift-Region Trench MOSFET With Improved Breakdown Voltage by Saxena, R.S., Kumar, M.J.

“…In this letter, we propose a new trench-gate power MOSFET with buried oxide in its drift region that shows an improvement in the breakdown performance as…”
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Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon-Germanium-on-Insu lator (SGOI) MOSFETs by Venkataraman, V., Nawal, S., Kumar, M.J.

“…In this paper, a physically based analytical threshold-voltage model is developed for nanoscale strained-Si on silicon-germanium-on-insulator MOSFETs for the…”
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Molecular diodes and applications by Kumar, M Jagadesh

“…Due to the huge power consumption and expensive fabrication methods required, down scaling silicon devices to sub-100 nm dimensions is becoming very…”
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Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis by Saurabh, Sneh, Kumar, M. Jagadesh

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