Search Results - "JUNGDAL CHOI"
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1
What Lies Ahead for Resistance-Based Memory Technologies?
Published in Computer (Long Beach, Calif.) (01-08-2013)“…Phase-change RAM, magnetic RAM, and resistive RAM offer strong scalability, speed, and power consumption advantages over conventional capacitance-based memory…”
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Journal Article -
2
3D approaches for non-volatile memory
Published in 2011 Symposium on VLSI Technology - Digest of Technical Papers (01-06-2011)“…The NAND flash market is continuously growing by the successive introduction of innovative devices and applications. To meet the market trend, 3-dimenstional…”
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Conference Proceeding -
3
A Novel nand Flash Memory With Asymmetric S/D Structure Using Fringe-Field-Induced Inversion Layer
Published in IEEE transactions on electron devices (01-01-2008)“…A NAND flash memory device for sub-40-nm-node technology and beyond utilizing an asymmetric source/drain (S/D) structure to suppress short-channel effects and…”
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4
Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory
Published in IEEE transactions on nanotechnology (01-03-2012)“…A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that…”
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5
Effects of Lateral Charge Spreading on the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory
Published in 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual (01-04-2007)“…It was found that the charge loss behavior of TANOS (TaN-Al 2 O 3 -nitride-oxide-silicon) cells for NAND flash memory application is highly dependent on the…”
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6
Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure
Published in 2008 Symposium on VLSI Technology (01-06-2008)“…The symmetric inversion-type S/D structure has been employed for achieving available program disturbance for scaled NAND flash memory beyond sub-40 nm node…”
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7
Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure
Published in 2010 Symposium on VLSI Technology (01-06-2010)“…The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a…”
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8
A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory
Published in 2010 Symposium on VLSI Technology (01-06-2010)“…A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics…”
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9
New phenomena for the Lifetime Prediction of TANOS-based Charge Trap NAND Flash Memory
Published in 68th Device Research Conference (01-06-2010)“…In this paper, the data retention characteristics of the charge trap flash (CTF) memory are evaluated and new findings to predict its lifetime more accurately…”
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10
A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM)
Published in 2012 International Electron Devices Meeting (01-12-2012)“…A non-linear RRAM cell with sub-1μA ultralow operating current has been successfully fabricated for high density vertical ReRAM (VRRAM) applications. A uniform…”
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Conference Proceeding -
11
Comparison of double patterning technologies in NAND flash memory with sub-30nm node
Published in 2009 Proceedings of the European Solid State Device Research Conference (01-09-2009)“…Fine patterning technologies - e-beam lithography, SPT (spacer patterning technology) and SaDPT (self aligned double patterning technology)-have been…”
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12
Future Outlook of NAND Flash Technology for 40nm Node and Beyond
Published in 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop (2006)“…The NAND flash memory occupied 40% of the total flash memory market with an annual growth rate of 70% in 2004, while NOR flash achieved only more modest growth…”
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13
A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies
Published in 2013 IEEE International Electron Devices Meeting (01-12-2013)“…This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC…”
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Conference Proceeding Journal Article -
14
What Lies Ahead for Resistance-Based Memory Technologies? : Next-Generation Memory
Published in Computer (Long Beach, Calif.) (2013)Get full text
Journal Article -
15
Endurance Prediction of Scaled NAND Flash Memory Based on Spatial Mapping of Erase Tunneling Current
Published in 2011 3rd IEEE International Memory Workshop (IMW) (01-05-2011)“…In this work, we present novel endurance prediction technique for scaled NAND Flash memory with arbitrary size and shape. Predicted endurance curve is obtained…”
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28.2 A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers \mathsf
Published in 2023 IEEE International Solid- State Circuits Conference (ISSCC) (19-02-2023)“…As data produced by multimedia explodes and demand for data storage increases, the most important topics for the NAND-Flash memory field are continuous…”
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17
Physical Modeling and Analysis on Improved Endurance Behavior of P-Type Floating Gate NAND Flash Memory
Published in 2012 4th IEEE International Memory Workshop (01-05-2012)“…In this work, we report improved endurance of p-type floating-gate NAND flash cell. The physical model on the endurance and data retention of p-type…”
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18
A New Cell-to-Cell Interference Induced by Conduction Band Distortion near S/D Region in Scaled NAND Flash Memories
Published in 2011 3rd IEEE International Memory Workshop (IMW) (01-05-2011)“…A new cell-to-cell interference phenomenon has been found beyond sub 40nm node. Unlike capacitive coupling between floating gates, the threshold voltage (V TH…”
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19
A New Cell-Type String Select Transistor in NAND Flash Memories for under 20nm Node
Published in 2012 4th IEEE International Memory Workshop (01-05-2012)“…A new string structure, having a cell-type string select transistor line (CT-SSL) is proposed for NAND flash memories beyond 20nm node device. The boosted…”
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20
A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density
Published in 2022 IEEE International Solid-State Circuits Conference (ISSCC) (20-02-2022)“…Triple-level-cell (TLC) NAND has prevailed the non-volatile memory market, yet the quad-level-cell (QLC) NAND is emerging as a suitable replacement for…”
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Conference Proceeding