Search Results - "JUNGDAL CHOI"

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  1. 1

    What Lies Ahead for Resistance-Based Memory Technologies? by Song, Yoon-Jong, Jeong, Gitae, Baek, In-Gyu, Choi, Jungdal

    Published in Computer (Long Beach, Calif.) (01-08-2013)
    “…Phase-change RAM, magnetic RAM, and resistive RAM offer strong scalability, speed, and power consumption advantages over conventional capacitance-based memory…”
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    Journal Article
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    3D approaches for non-volatile memory by Jungdal Choi, Kwang Soo Seol

    “…The NAND flash market is continuously growing by the successive introduction of innovative devices and applications. To meet the market trend, 3-dimenstional…”
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    Conference Proceeding
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    A Novel nand Flash Memory With Asymmetric S/D Structure Using Fringe-Field-Induced Inversion Layer by PARK, Ki-Tae, SEL, Jong-Sun, CHOI, Jungdal, SONG, Yunheub, KIM, Changhyun, KIM, Kinam

    Published in IEEE transactions on electron devices (01-01-2008)
    “…A NAND flash memory device for sub-40-nm-node technology and beyond utilizing an asymmetric source/drain (S/D) structure to suppress short-channel effects and…”
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    Journal Article
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    Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory by SHIM, Won Bo, CHO, Seongjae, PARK, Byung-Gook, LEE, Jung Hoon, LI, Dong Hua, KIM, Doo-Hyun, LEE, Gil Sung, KIM, Yoon, PARK, Se Hwan, KIM, Wandong, CHOI, Jungdal

    Published in IEEE transactions on nanotechnology (01-03-2012)
    “…A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that…”
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    Journal Article
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    Effects of Lateral Charge Spreading on the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory by Changseok Kang, Jungdal Choi, Jaesung Sim, Changhyun Lee, Yoocheol Shin, Jintaek Park, Jongsun Sel, Sanghun Jeon, Youngwoo Park, Kinam Kim

    “…It was found that the charge loss behavior of TANOS (TaN-Al 2 O 3 -nitride-oxide-silicon) cells for NAND flash memory application is highly dependent on the…”
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    Conference Proceeding
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    Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure by Chang-Hyun Lee, Jungdal Choi, Youngwoo Park, Changseok Kang, Byeong-In Choi, Hyunjae Kim, Hyunsil Oh, Won-Seong Lee

    Published in 2008 Symposium on VLSI Technology (01-06-2008)
    “…The symmetric inversion-type S/D structure has been employed for achieving available program disturbance for scaled NAND flash memory beyond sub-40 nm node…”
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    Conference Proceeding
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    A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory by Kwang Soo Seol, Heesoo Kang, Jaeduk Lee, Hyunsuk Kim, Byungkyu Cho, Dohyun Lee, Yong-Lack Choi, Nok-Hyun Ju, Changmin Choi, SungHoi Hur, Jungdal Choi, Chilhee Chung

    Published in 2010 Symposium on VLSI Technology (01-06-2010)
    “…A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics…”
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    Conference Proceeding
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    New phenomena for the Lifetime Prediction of TANOS-based Charge Trap NAND Flash Memory by Juhyung Kim, Changseok Kang, Sung-Il Chang, Jongyeon Kim, Younseok Jeong, Chan Park, Joo-Heon Kang, Sang-Hoon Kim, Sunkyu Hwang, Byeong-In Choe, Jintaek Park, Juhyuck Chung, Youngwoo Park, Jungdal Choi, Chilhee Chung

    Published in 68th Device Research Conference (01-06-2010)
    “…In this paper, the data retention characteristics of the charge trap flash (CTF) memory are evaluated and new findings to predict its lifetime more accurately…”
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    Conference Proceeding
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    A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM) by Seong-Geon Park, Min Kyu Yang, Hyunsu Ju, Dong-Jun Seong, Jung Moo Lee, Eunmi Kim, Seungjae Jung, Lijie Zhang, Yoo Cheol Shin, In-Gyu Baek, Jungdal Choi, Ho-Kyu Kang, Chilhee Chung

    “…A non-linear RRAM cell with sub-1μA ultralow operating current has been successfully fabricated for high density vertical ReRAM (VRRAM) applications. A uniform…”
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    Conference Proceeding
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    Comparison of double patterning technologies in NAND flash memory with sub-30nm node by Byungjoon Hwang, Jeehoon Han, Myeong-Cheol Kim, Sunggon Jung, Namsu Lim, Sowi Jin, Yongsik Yim, Donghwa Kwak, Jaekwan Park, Jungdal Choi, Kinam Kim

    “…Fine patterning technologies - e-beam lithography, SPT (spacer patterning technology) and SaDPT (self aligned double patterning technology)-have been…”
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    Conference Proceeding
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    Future Outlook of NAND Flash Technology for 40nm Node and Beyond by Kinam Kim, Jungdal Choi

    “…The NAND flash memory occupied 40% of the total flash memory market with an annual growth rate of 70% in 2004, while NOR flash achieved only more modest growth…”
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    Conference Proceeding
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    A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies by Hur, Sung-Gi, Yang, Jung-Gil, Kim, Sang-Su, Lee, Dong-Kyu, An, Taehyun, Nam, Kab-Jin, Kim, Seong-Je, Wu, Zhenhua, Lee, Wonsok, Kwon, Uihui, Lee, Keun-Ho, Park, Youngkwan, Yang, Wouns, Choi, Jungdal, Kang, Ho-Kyu, Jung, EunSung

    “…This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC…”
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    Conference Proceeding Journal Article
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    Endurance Prediction of Scaled NAND Flash Memory Based on Spatial Mapping of Erase Tunneling Current by Fayrushin, A, ChangHyun Lee, Youngwoo Park, Jungdal Choi, Jeonghyuk Choi, Chilhee Chung

    “…In this work, we present novel endurance prediction technique for scaled NAND Flash memory with arbitrary size and shape. Predicted endurance curve is obtained…”
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    Conference Proceeding
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    Physical Modeling and Analysis on Improved Endurance Behavior of P-Type Floating Gate NAND Flash Memory by ChangHyun Lee, Fayrushin, A., Sunghoi Hur, Youngwoo Park, Jungdal Choi, Jeonghyuk Choi, Chilhee Chung

    “…In this work, we report improved endurance of p-type floating-gate NAND flash cell. The physical model on the endurance and data retention of p-type…”
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    Conference Proceeding
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    A New Cell-to-Cell Interference Induced by Conduction Band Distortion near S/D Region in Scaled NAND Flash Memories by Byungkyu Cho, ChangHyun Lee, Kwangsoo Seol, Sunghoi Hur, Jungdal Choi, Jeonghyuk Choi, Chilhee Chung

    “…A new cell-to-cell interference phenomenon has been found beyond sub 40nm node. Unlike capacitive coupling between floating gates, the threshold voltage (V TH…”
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    Conference Proceeding
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    A New Cell-Type String Select Transistor in NAND Flash Memories for under 20nm Node by Do-Hyune Lee, Yoocheol Shin, Donghoon Jang, Changhyun Lee, Joon-Hee Lee, Jungdal Choi, Seong-Soon Cho, Jeong-Hyuk Choi

    “…A new string structure, having a cell-type string select transistor line (CT-SSL) is proposed for NAND flash memories beyond 20nm node device. The boosted…”
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    Conference Proceeding
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