Search Results - "JUNG-SUK GOO"

Foreword Special Issue on Compact Modeling of Semiconductor Devices by Iniguez, Benjamin, Chauhan, Yogesh Singh, Mijalkovic, Slobodan, Xia, Kejun, Goo, Jung-Suk, Pavanello, Marcelo, Mierzwinski, Marek, Grabinski, Wladek

“…This Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact…”
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A noise optimization technique for integrated low-noise amplifiers by Jung-Suk Goo, Hee-Tae Ahn, Ladwig, D.J., Zhiping Yu, Lee, T.H., Dutton, R.W.

“…Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are…”
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Band offset induced threshold variation in strained-Si nMOSFETs by Jung-Suk Goo, Qi Xiang, Takamura, Y., Arasnia, F., Paton, E.N., Besser, P., Pan, J., Ming-Ren Lin

“…Due to the offset in the valence band, strained-Si nMOSFETs exhibit a -100 mV threshold shift and 4% degradation of the subthreshold slope per each 10%…”
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Scalability of strained-Si nMOSFETs down to 25 nm gate length by Jung-Suk Goo, Qi Xiang, Takamura, Y., Haihong Wang, Pan, J., Arasnia, F., Paton, E.N., Besser, P., Sidorov, M.V., Adem, E., Lochtefeld, A., Braithwaite, G., Currie, M.T., Hammond, R., Bulsara, M.T., Ming-Ren Lin

“…Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference…”
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An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs by Jung-Suk Goo, Chang-Hoon Choi, Danneville, F., Morifuji, E., Momose, H.S., Zhiping Yu, Iwai, H., Lee, T.H., Dutton, R.W.

“…Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for…”
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Capacitance reconstruction from measured C-V in high leakage, nitride/oxide MOS by Chang-Hoon Choi, Wu, Y., Jung-Suk Goo, Zhiping Yu, Dutton, R.W.

“…A reconstruction technique of the gate capacitance from anomalous capacitance-voltage (C-V) curves in high leakage dielectric MOSFETs is presented. An RC…”
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Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection by Vyas, Pratik B., Pimparkar, Ninad, Tu, Robert, Arfaoui, Wafa, Bossu, Germain, Siddabathula, Mahesh, Lehmann, Steffen, Goo, Jung-Suk, Icel, Ali B.

“…Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so…”
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MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm) by Chang-Hoon Choi, Jung-Suk Goo, Tae-Young Oh, Zhiping Yu, Dutton, R.W., Bayoumi, A., Min Cao, Voorde, P.V., Vook, D., Diaz, C.H.

“…An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including…”
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Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length by Jung-Suk Goo, Mantei, T., Wieczorek, K., En, W.G., Icel, A.B.

“…This letter demonstrates that the conventional two-element lumped model can provide valid capacitance-voltage (C-V ) characteristics for gate oxides with large…”
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The effect of annealing temperatures on self-aligned replacement (damascene) TaCN-TaN-stacked gate pMOSFETs by Pan, J., Woo, C., Ngo, M.-V., Xie, J., Matsumoto, D., Murthy, D., Jung-Suk Goo, Qi Xiang, Ming-Ren Lin

“…In this paper, we report the first self-aligned replacement (Damascene) TaCN-TaN-stacked gate electrode pMOSFETs. The high-temperature (>1000/spl deg/C)…”
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SIS wide-band model extraction methodology for SOI on-chip inductor by Topaloglu, Rasit Onur, Jung-Suk Goo, Loke, Alvin L S, Oshima, Michael M, Sim, Sam Wonsae

“…On-chip inductors are recently in high demand even for digital applications due to strict jitter and phase noise requirements in oscillators. Accurate and fast…”
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Physical origin of the excess thermal noise in short channel MOSFETs by Jung-Suk Goo, Chang-Hoon Choi, Abramo, A., Jae-Gyung Ahn, Zhiping Yu, Lee, T.H., Dutton, R.W.

“…The physical origin of the excess thermal noise in short channel MOSFETs is explained based on numerical noise simulation. The impedance field representation…”
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Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges by Jung-Suk Goo, Williams, R.Q., Workman, G.O., Qiang Chen, Sungjae Lee, Nowak, E.J.

“…This paper reviews the status and challenges of the modeling partially-depleted silicon-on-insulator transistors. Many challenges stem from the floating-body…”
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Shallow source/drain extension effects on external resistance in sub-0.1 μm MOSFETs by Chang-Hoon Choi, Jung-Suk Goo, Zhiping Yu, Dutton, R.W.

“…Accurate external resistance extraction for shallow source/drain extension (SDE) MOSFET's is demonstrated using a unified mobility model for inversion and…”
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Switching-mode dependence of inductive noise in VLSI power bus lines by Jung-Suk Goo, Hale, S., Zamudio, L., Pelella, M.M., Klein, R., Butler, S., Judy Xilin An, Lee, M., Icel, A.B.

“…The switching-mode dependence of inductive noise on the power bus lines has been investigated. As the maximum operation frequency of the very large-scale…”
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Impact of stress on various circuit characteristics in 65nm PDSOI technology by Suryagandh, S., Gupta, M., Zhi-Yuan Wu, Krishnan, S., Pelella, M., Jung-Suk Goo, Thuruthiyil, C., An, J.X., Chen, B.Q., Subba, N., Zamudio, L., Yonemura, J., Icel, A.B.

“…Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a…”
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Impact of stress on various circuit characteristics in 65nm PDSOI technology by Suryagandh, S., Gupta, M., Zhi-Yuan Wu, Krishnan, S., Pelella, M., Jung-Suk Goo, Thuruthiyil, C., An, J.X., Chen, B.Q., Subba, N., Zamudio, L., Yonemura, J., Icel, A.B.

“…Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a…”
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An analytical model for hot-carrier-induced degradation of deep-submicron n-channel LDD MOSFETs by Goo, Jung-Suk, Kim, Young-Gwan, L'Yee, Hyeokjae, Kwon, Ho-Yup, Shin, Hyungsoon

“…A universal behavior of hot-carrier-induced degradation of n-channel LDD MOSFETs has been modeled for the first time. This new physical model is based on…”
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Physical analysis for saturation behavior of hot-carrier degradation in lightly doped drain N-channel metal-oxide-semiconductor field effect transistors by JUNG-SUK GOO, HYUNGSOON SHIN, HYUNSANG HWANG, DAE-GWAN KANG, DONG-HYUK JU

“…This paper experimentally demonstrates that hot carrier degradation curves of lightly doped drain n-channel metal-oxide-semiconductor field effect transistors…”
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Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variables by Bo Yu, Xin Li, Yonemura, J., Zhiyuan Wu, Jung-Suk Goo, Thuruthiyil, C., Icel, A.

“…In this paper, we investigate the geometry dependence for the local variation of low-frequency noise in MOSFETs via the sum of lognormal random variables. A…”
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