Search Results - "JEON, Kanghoon"

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    Si tunnel transistors with a novel silicided source and 46mV/dec swing by Kanghoon Jeon, Wei-Yip Loh, Patel, P, Chang Yong Kang, Jungwoo Oh, Bowonder, A, Chanro Park, Park, C S, Smith, C, Majhi, P, Hsing-Huang Tseng, Jammy, R, Liu, Tsu-Jae King, Chenming Hu

    Published in 2010 Symposium on VLSI Technology (01-06-2010)
    “…We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special…”
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    Conference Proceeding
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    Comprehensive Study of Quasi-Ballistic Transport in High- \kappa/Metal Gate nMOSFETs by Hyun Chul Sagong, Chang Yong Kang, Chang-Woo Sohn, Kanghoon Jeon, Eui-Young Jeong, Do-Young Choi, Chang-Ki Baek, Jeong-Soo Lee, Lee, J. C., Yoon-Ha Jeong

    Published in IEEE electron device letters (01-11-2011)
    “…We study quasi-ballistic transport in nanoscale high-κ/metal gate nMOSFETs based on radio-frequency (RF) S -parameter analysis. An RF S -parameter-based simple…”
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    Journal Article
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    Palladium/silicon nanowire Schottky barrier-based hydrogen sensors by Skucha, Karl, Fan, Zhiyong, Jeon, Kanghoon, Javey, Ali, Boser, Bernhard

    Published in Sensors and actuators. B, Chemical (04-03-2010)
    “…This work presents the design, fabrication, and characterization of a hydrogen sensor based on a palladium/nanowire Schottky barrier field-effect transistor…”
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    Journal Article
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    A Low Voltage Steep Turn-Off Tunnel Transistor Design by Patel, P., Kanghoon Jeon, Bowonder, A., Chenming Hu

    “…A new tunneling transistor structure is introduced that offers several advantages over prior designs. Notably, tunneling area is substantially increased. Turn…”
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    Conference Proceeding
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    Prospect of tunneling green transistor for 0.1V CMOS by Chenming Hu, Patel, P, Bowonder, A, Kanghoon Jeon, Sung Hwan Kim, Wei Yip Loh, Chang Yong Kang, Jungwoo Oh, Majhi, P, Javey, A, Tsu-Jae King Liu, Jammy, R

    “…Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8"…”
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    Conference Proceeding
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    Low-voltage green transistor using ultra shallow junction and hetero-tunneling by Bowonder, A., Patel, P., Kanghoon Jeon, Jungwoo Oh, Majhi, P., Hsing-Huang Tseng, Chenming Hu

    “…A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage…”
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    Conference Proceeding
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    High mobility CMOS transistors on Si/SiGe heterostructure channels by Oh, Jungwoo, Jeon, Kanghoon, Lee, Se-Hoon, Huang, Jeff, Hung, P.Y., Ok, Injo, Sassman, Barry, Ko, Dae-Hong, Kirsch, Paul, Jammy, Raj

    Published in Microelectronic engineering (01-09-2012)
    “…We have demonstrated high mobility CMOS transistors on Si/SiGe heterostructure channels selectively grown on a Si (100) substrate. Electron and hole mobility…”
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    Journal Article
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    Band-to-Band Tunnel Transistor Design and Modeling for Low Power Applications by Jeon, Kanghoon

    Published 01-01-2012
    “…As the physical dimensions of the MOSFET have been scaling, the supply voltage has not scaled accordingly and thus the power density has been continuously…”
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    Dissertation
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    Tri-gate bulk MOSFET design for improved robustness to random dopant fluctuations by Changhwan Shin, Carlson, A., Xin Sun, Kanghoon Jeon, Tsu-Jae King Liu

    Published in 2008 IEEE Silicon Nanoelectronics Workshop (01-06-2008)
    “…Atomistic 3D device simulations of 20nm-gate-length planar vs. tri-gate bulk MOSFETs with identical nominal retrograde-well and source/drain doping profiles…”
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    Conference Proceeding
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    Highly scaled (Lg∼56nm) gate-last Si tunnel field-effect transistors with ION>100μA/μm by Loh, Wei-Yip, Jeon, Kanghoon, Kang, Chang Yong, Oh, Jungwoo, King Liu, Tsu-Jae, Tseng, Hsing-Huang, Xiong, Wade, Majhi, Prashant, Jammy, Raj, Hu, Chenming

    Published in Solid-state electronics (01-11-2011)
    “…Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly…”
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    Journal Article Conference Proceeding
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    Comprehensive Study of Quasi-Ballistic Transport in High-[Formula Omitted]/Metal Gate nMOSFETs by Sagong, Hyun Chul, Kang, Chang Yong, Sohn, Chang-Woo, Jeon, Kanghoon, Jeong, Eui-Young, Choi, Do-Young, Baek, Chang-Ki, Lee, Jeong-Soo, Lee, Jack C, Jeong, Yoon-Ha

    Published in IEEE electron device letters (01-11-2011)
    “…We study quasi-ballistic transport in nanoscale high-[Formula Omitted]/metal gate nMOSFETs based on radio-frequency (RF) [Formula Omitted] -parameter analysis…”
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    Journal Article
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    Highly scaled (L sub(g [approx] 56 nm) gate-last Si tunnel field-effect transistors with I) sub(O)N 100 mu A/ mu m by Loh, Wei-Yip, Jeon, Kanghoon, Kang, Chang Yong, Oh, Jungwoo, Liu, Tsu-Jae King, Tseng, Hsing-Huang, Xiong, Wade, Majhi, Prashant, Jammy, Raj, Hu, Chenming

    Published in Solid-state electronics (01-12-2011)
    “…Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly…”
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    Journal Article
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    Sub-5nm All-Around Gate FinFET for Ultimate Scaling by Lee, H., Yu, L.-E., Ryu, S.-W., Han, J.-W., Jeon, K., Jang, D.-Y., Kim, K.-H., Lee, J., Kim, J.-H., Jeon, S., Lee, G., Oh, J., Park, Y., Bae, W., Lee, H., Yang, J., Yoo, J., Kim, S., Choi, Y.-K.

    “…Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO 2 shows an I Dsat of…”
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    Conference Proceeding
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    Band-to-Band Tunnel Transistor Design and Modeling for Low Power Applications by Jeon, Kanghoon

    “…As the physical dimensions of the MOSFET have been scaling, the supply voltage has not scaled accordingly and thus the power density has been continuously…”
    Get full text
    Dissertation