Search Results - "JAIN, F. C"

Ge-ZnSSe Spatial Wavefunction Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic by Gogna, P., Suarez, E., Lingalugari, M., Chandy, J., Heller, E., Hasaneen, E.-S., Jain, F.-C.

“…This paper describes novel multibit static random-access memories (SRAMs) implemented using four-channel spatial wavefunction switched field-effect transistors…”
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Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators by Lingalugari, M., Baskar, K., Chan, P.-Y., Dufilie, P., Suarez, E., Chandy, J., Heller, E., Jain, F. C.

“…Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiO x -cladded Si or GeO x -cladded Ge…”
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Spatial Wavefunction-Switched (SWS) InGaAs FETs with II–VI Gate Insulators by Jain, F. C., Miller, B., Suarez, E., Chan, P.-Y., Karmakar, S., Al-Amoody, F., Gogna, M., Chandy, J., Heller, E.

“…This paper presents the implementation of a novel InGaAs field-effect transistor (FET), using a ZnSe-ZnS-ZnMgS-ZnS stacked gate insulator, in a spatial…”
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Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators by Jain, F. C., Suarez, E., Gogna, M., Alamoody, F., Butkiewicus, D., Hohner, R., Liaskas, T., Karmakar, S., Chan, P.-Y., Miller, B., Chandy, J., Heller, E.

“…This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of…”
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The role of H2O2 outer diffusion on the performance of implantable glucose sensors by VADDIRAJU, S, BURGESS, D. J, JAIN, F. C, PAPADIMITRAKOPOULOS, F

“…The performance of an implantable glucose sensor is strongly dependent on the ability of their outer membrane to govern the diffusion of the various…”
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Fabrication and Simulation of an Indium Gallium Arsenide Quantum-Dot-Gate Field-Effect Transistor (QDG-FET) with ZnMgS as a Tunnel Gate Insulator by Chan, P.-Y., Gogna, M., Suarez, E., Al-Amoody, F., Karmakar, S., Miller, B. I., Heller, E. K., Ayers, J. E., Jain, F. C.

“…An indium gallium arsenide quantum-dot-gate field-effect transistor using Zn 0.95 Mg 0.05 S as the gate insulator is presented in this paper, showing three…”
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S-Graded Buffer Layers for Lattice-Mismatched Heteroepitaxial Devices by Xhurxhi, S., Obst, F., Sidoti, D., Bertoli, B., Kujofsa, T., Cheruku, S., Correa, J. P., Rago, P. B., Suarez, E. N., Jain, F. C., Ayers, J. E.

“…We have conducted a theoretical study of the equilibrium strain and misfit dislocation density profiles for “S-graded” buffer layers of In x Ga 1− x As on GaAs…”
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Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior by Chan, P.-Y., Suarez, E., Gogna, M., Miller, B.I., Heller, E.K., Ayers, J.E., Jain, F.C.

“…This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “ i ” state in…”
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Overshoot Graded Layers for Mismatched Heteroepitaxial Devices by Ocampo, J.F., Suarez, E., Jain, F.C., Ayers, J.E.

“…We have studied the use of overshoot graded layers for the control of the dislocation density in mismatched heteroepitaxial layers. Graded ZnS y Se 1– y…”
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Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators by Chan, P.-Y., Gogna, M., Suarez, E., Karmakar, S., Al-Amoody, F., Miller, B. I., Jain, F. C.

“…This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and…”
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Critical Layer Thickness in Exponentially Graded Heteroepitaxial Layers by Sidoti, D., Xhurxhi, S., Kujofsa, T., Cheruku, S., Reed, J., Bertoli, B., Rago, P. B., Suarez, E. N., Jain, F. C., Ayers, J. E.

“…Exponentially graded semiconductor layers are of interest for use as buffers in heteroepitaxial devices because of their tapered dislocation density and strain…”
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A quantitative model for the interpretation of RAV (rocking curve azimuthal variation) results from heteroepitaxial semiconductor layers by Yarlagadda, B., Rodriguez, A., Li, P., Velampati, R., Ocampo, J.F., Ayers, J.E., Jain, F.C.

“…Here we present a new quantitative model for the interpretation of the asymmetric broadening of the full width at half maximum (FWHM) of X-ray rocking curves…”
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An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors by Mirdha, P., Parthasarathy, B., Kondo, J., Chan, P.-Y., Heller, E., Jain, F. C.

“…Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p -type substrate to form a QD superlattice (QDSL). The QDSL…”
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Elastic strains in heteroepitaxial ZnSe1-xTex on InGaAs/InP (001) by YARLAGADDA, B, RODRIGUEZ, A, LI, P, MILLER, B. I, JAIN, F. C, AYERS, J. E

“…Here we report on the elastic strains in ZnSe1-xTex (x < 0.9) epitaxial layers grown using photo-assisted metalorganic vapor phase epitaxy on…”
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Effect of Epilayer Tilt on Dynamical X-ray Diffraction from Uniform Heterostructures with Asymmetric Dislocation Densities by Rago, P.B., Jain, F.C., Ayers, J.E.

“…In this work we extend the dynamical theory of Bragg x-ray diffraction to account for a tilted, asymmetrically defected, uniform-composition epitaxial layer…”
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Relaxation Dynamics and Threading Dislocations in ZnSe and ZnSySe1−y/GaAs (001) Heterostructures by Kujofsa, T., Cheruku, S., Yu, W., Outlaw, B., Xhurxhi, S., Obst, F., Sidoti, D., Bertoli, B., Rago, P. B., Suarez, E. N., Jain, F. C., Ayers, J. E.

“…The design of lattice-mismatched semiconductor devices requires a predictive model for strains and threading dislocation densities. Previous work enabled…”
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Plastic Flow and Dislocation Compensation in ZnSySe1−y/GaAs (001) Heterostructures by Kujofsa, T., Yu, W., Cheruku, S., Outlaw, B., Xhurxhi, S., Obst, F., Sidoti, D., Bertoli, B., Rago, P.B., Suarez, E.N., Jain, F.C., Ayers, J.E.

“…An important goal of lattice-mismatched semiconductor device design is control of threading dislocation densities, which are of particular importance for…”
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Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices by Li, P., Rodriguez, A., Yarlagadda, B., Velampati, R., Ayers, J.E., Jain, F.C.

“…MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an…”
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Comparison of X-ray diffraction methods for determination of the critical layer thickness for dislocation multiplication by ZHANG, X. G, LI, P, PARENT, D. W, ZHAO, G, AYERS, J. E, JAIN, F. C

“…We present a comparison of x-ray diffraction methods for the determination of the critical layer thickness for dislocation multiplication in mismatched…”
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X-ray characterization of dislocation density asymmetries in heteroepitaxial semiconductors by Yarlagadda, B., Rodriguez, A., Li, P., Velampati, R., Ocampo, J. F., Suarez, E. N., Rago, P. B., Shah, D., Ayers, J. E., Jain, F. C.

“…We demonstrate an x-ray rocking curve method which allows detection of an asymmetry in the dislocation densities in an heteroepitaxial (001) zinc blende…”
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