A high speed FPGA implementation of the Rijndael algorithm

This paper presents a high speed, non-pipelined FPGA implementation of the Rijndael algorithm (Daemen, 1999), which has been selected as the new AES algorithm by the National Institute of Standards and Technology (NIST). In this study, we have implemented both the encryption and the decryption algor...

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Bibliographic Details
Published in:	Euromicro Symposium on Digital System Design, 2004. DSD 2004 pp. 358 - 362
Main Authors:	Sever, R., Ismailglu, A.N., Tekmen, Y.C., Askar, M., Okcan, B.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 2004
Subjects:	Algorithm design and analysis Application specific integrated circuits Cryptography Design optimization Feedback Field programmable gate arrays Frequency NIST Pipelines Throughput
Online Access:	Get full text
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Summary:	This paper presents a high speed, non-pipelined FPGA implementation of the Rijndael algorithm (Daemen, 1999), which has been selected as the new AES algorithm by the National Institute of Standards and Technology (NIST). In this study, we have implemented both the encryption and the decryption algorithms of Rijndael on the same FPGA. All the key and data length combinations of the original Rijndael algorithm are supported. This implementation, which uses 8378 slices and 4 block RAMs of the Xilinx FPGA, has a worst case operating frequency of 65 MHz, yielding a maximum throughput of 1.19 Gb/s.
ISBN:	9780769522036 0769522033
DOI:	10.1109/DSD.2004.1333297