Search Results - "International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)"

Development of environmental friendly (green), thermally enhanced mold compound (TEMC) for advanced packages by Tan, T.H., Mogi, N., Yeoh, L.P.

“…This paper outlines the development and performance of a new series of mold compounds with thermal conductivity (/spl lambda/) up to 100/spl times/10/sup -4/…”
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Moisture sensor using reactive sputtered TiO/sub 2/ thin film with negative substrate bias by Chow, L.L.W., Yuen, M.M.F., Chan, P.C.H., Teng, A.

“…Moisture is known as a major factor in degrading the reliability of electronic packages. It is estimated that over 40% of failures in electronic devices are…”
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A new method using energy release elements for evaluating bonding strength [packaging] by Hatsuda, T., Minamitani, R.

“…We have developed a new method, based on the concept of energy release rate, for evaluating bonding strength. This method uses a finite element approach and…”
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Thermal deformations of CSP assembly during temperature cycling and power cycling by Ham, S.J., Cho, M.S., Lee, S.B.

“…In this paper, thermal deformations of CSP assemblies during temperature cycling and power cycling were investigated using high sensitivity moire…”
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Sintering process of low temperature cofired ceramics by Han, Z., Ma, J., Xu, Z., Wang, Q., Huang, L., Li, Y.

“…In order to research the mismatch shrinkage between a package substrate and metal lines, this paper studies the sintering densification process of low…”
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A method to quantify the surface insulation resistance performance of conformal coatings exposed to different temperature/humidity conditions by Tomlins, P.E.

“…Typical conformal coatings based on different chemistries and formulated by different manufacturers are selected for a particular application on the basis of a…”
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Board level solder joint reliability modeling of LFBGA package by Tong Yan Tee, Sivakumar, K., Do-Bento-Vieira, A.

“…In this paper, a 3D FEA sliced model is built for LFBGA (low profile fine pitch BGA) on board to predict the fatigue life of solder joints during thermal…”
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The effects of underfill and its material models on thermomechanical behaviors of flip chip package by Zhaonian Cheng, Liu Chen, Guozhong Wang, Xiaoming Xie, Qun Zhang

“…In this paper, underfill effects on thermomechanical behavior of two types (B and D) of flip chip packages with different bump sizes and stand-off heights were…”
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The study on the novel lead-free solder alloy by Huang Le, Wang Qian, Ma Jusheng

“…Sn-Pb solders are widely used in the electronics industry, but lead is to be restricted due to its toxicity. The properties of Sn-Ag-Cu and Sn-Ag-Zn system…”
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Reliability and failure analysis of voting circuits in hardware redundant design by Radu, M., Pitica, D., Posteuca, C.

“…This paper presents some aspects of fault-tolerant design using hardware redundancy. The voter is the key element in N-modular redundant design. Hardware…”
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Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP) by Lau, J.H., Lee, S.-W.R.

“…The creep analyses of solder-bumped wafer level chip scale packages (WLCSP) on build-up printed circuit boards (PCB) with microvias subjected to thermal cyclic…”
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Modelling the fatigue life of solder joints for surface mount resistors by Lu, H., Bailey, C., Dusek, M., Hunt, C., Nottay, J.

“…This paper discusses the results from a modelling study that is being undertaken to compliment a large-scale experimental programme currently underway at the…”
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Survey on delamination of IC packages in electronic products by Ho, K., Teng, A.

“…The electronics industry is concerned about the delamination of plastic-encapsulated IC packages to assure high product quality. Much effort has been invested…”
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Plasma cleaning of chip scale packages for improvement of wire bond strength by Wood, L., Fairfield, C., Wang, K.

“…As the integrated circuit becomes ever smaller, the associated decrease in size of the wire bond pad, on both the chip and leadframe or BGA, brings many new…”
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Laser-assisted bump transfer for flip chip assembly by Wang, C.H., Holmes, A.S., Gao, S.

“…This paper describes a novel laser-assisted bumping technique for flip chip assembly. Copper bumps, with gold bonding layers and intermediate nickel barriers,…”
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A new stress chip design for electronic packaging applications by Hau, W.L.W., Yuen, M.M.F., Yan, G.Z., Chan, P.C.H.

“…Stress sensing chips are invaluable for structural analysis of electronic packages, and can be used for in-situ real-time measurement of thermally induced die…”
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Electroless nickel bath for wafer bumping: influence of additives by Chen, X., Yi, J., Qi, G., Liu, F.

“…Aluminium bond pads on silicon wafers have two distinct features: small area and thin material. This necessitates special considerations for the design of the…”
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Influences of pad shape and solder microstructure on shear force of low cost flip chip bumps by Jian Cai, Law, S., Teng, A., Chan, P.C.H.

“…The bumping process plays a critical role in flip chip technology. A low cost bumping process has been developed using electroless nickel and immersion gold…”
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Low cost flip chip bumping by Oppert, T., Teutsch, T., Zakel, E.

“…Flip chip (FC) technology is a driving force for increased speed and performance along with higher I/O count, and has therefore a high level of importance for…”
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Simulation of the stencil printing process [solder pastes] by Glinski, G.P., Bailey, C., Pericleous, K.

“…This paper describes the application of advanced computational fluid dynamics (CFD) methods to model the stencil printing process at both macroscopic and…”
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