Search Results - "Ingelsson, Urban"

Test Planning for Core-based Integrated Circuits under Power Constraints by SenGupta, Breeta, Nikolov, Dimitar, Ingelsson, Urban, Larsson, Erik

“…This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under…”
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Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption by Ingelsson, Urban, Goel, Sandeep Kumar, Larsson, Erik, Marinissen, Erik Jan

“…System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass…”
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Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems by Nikolov, Dimitar, Ingelsson, Urban, Singh, Virendra, Larsson, Erik

“…•Use Level Of Confidence (LoC) as metric to evaluate to what extent a deadline is met.•Use LoC to evaluate both hard and soft real-time systems (RTS).•Optimize…”
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Access Time Analysis for IEEE P1687 by Zadegan, F. G., Ingelsson, U., Carlsson, G., Larsson, E.

“…The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip…”
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Scheduling Tests for 3D Stacked Chips under Power Constraints by SenGupta, Breeta, Ingelsson, Urban, Larsson, Erik

“…This paper addresses Test Application Time ( TAT ) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias…”
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Bridging Fault Test Method With Adaptive Power Management Awareness by Khursheed, S., Ingelsson, U., Rosinger, P., Al-Hashimi, B.M., Harrod, P.

“…A key design constraint of circuits used in hand-held devices is the power consumption, mainly due to battery-life limitations. Adaptive power management (APM)…”
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Process Variation-Aware Test for Resistive Bridges by Ingelsson, U., Al-Hashimi, B.M., Khursheed, S., Reddy, S.M., Harrod, P.

“…This paper analyzes the behavior of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality…”
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Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints by Zadegan, F. G., Ingelsson, U., Asani, G., Carlsson, G., Larsson, E.

“…In contrast to IEEE 1149.1, IEEE P1687 allows, through segment insertion bits, flexible scan paths for accessing on-chip instruments, such as test, debug,…”
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Test Time Analysis for IEEE P1687 by Zadegan, F G, Ingelsson, U, Carlsson, G, Larsson, E

“…The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and…”
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Investigation into voltage and process variation-aware manufacturing test by Ingelsson, U., Al-Hashimi, B. M.

“…Traditional test methods that use abstract fault models potentially results in low defect coverage and test escapes for ICs with multiple supply voltage (Vdd)…”
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Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias by SenGupta, B., Ingelsson, U., Larsson, E.

“…Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule…”
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Efficient Embedding of Deterministic Test Data by Majeed, M, Ahlström, Daniel, Ingelsson, U, Carlsson, G, Larsson, E

“…Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in…”
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Design automation for IEEE P1687 by Zadegan, F G, Ingelsson, U, Carlsson, G, Larsson, E

“…The IEEE P1687 (IJTAG) standard proposal aims at standardizing the access to embedded test and debug logic (instruments) via the JTAG TAP. P1687 specifies a…”
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Variation Aware Analysis of Bridging Fault Testing by Ingelsson, U., Al-Hashimi, B.M., Harrod, P.

“…This paper investigates the impact of process variation on test quality with regard to resistive bridging faults. The input logic threshold voltage and gate…”
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Resistive Bridging Faults DFT with Adaptive Power Management Awareness by Ingelsson, U., Rosinger, P., Khursheed, S.S., Al-Hashimi, B.M., Harrod, P.

“…A key design constraint of circuits used in handheld devices is the power consumption, due mainly to the limitations of battery life. The employment of…”
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Addressing model complexity in automotive system development: Selection of system model elements for allocation of requirements by Liebel, Grischa, Olaru, Andreea, Lonn, Henrik, Kaijser, Henrik, Rajendran, Sunith, Ingelsson, Urban, Svensson, Richard Berntsson

“…Modern automotive embedded systems are developed by Original Equipment Manufacturers (OEM) together with multiple suppliers. A key problem for a supplier is to…”
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Fault injection and fault handling: An MPSoC demonstrator using IEEE P1687 by Petersen, Kim, Nikolov, Dimitar, Ingelsson, Urban, Carlsson, Gunnar, Zadegan, Farrokh Ghani, Larsson, Erik

“…As fault handling in multi-processor system-on-chips (MPSoCs) is a major challenge, we have developed an MPSoC demonstrator that enables experimentation on…”
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Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687 by Ghani Zadegan, Farrokh, Ingelsson, U., Larsson, E., Carlsson, G.

“…This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE P1687 standard in an era where reuse of existing functional…”
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Test tool qualification through fault injection by Wang, Q., Wallin, A., Izosimov, V., Ingelsson, U., Peng, Z.

“…According to ISO 26262, a recent automotive functional safety standard, verification tools shall undergo qualification, e.g. to ensure that they do not fail to…”
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Scheduling Tests for 3D Stacked Chips under Power Constraints by Sen Gupta, Breeta, Ingelsson, U, Larsson, E

“…This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for…”
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