Search Results - "Ilderem, V."

Floating body induced pre-kink excess low-frequency noise in submicron SOI CMOSFET technology by Ying-Che Tseng, Huang, W.M., Ilderem, V., Woo, J.C.S.

“…The well-known post-kink Lorentzian-like noise overshoot has been empirically correlated to the ac kink effect in the SOI CMOSFET in the past. This work…”
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Very low pressure chemical vapor deposition process for selective titanium silicide films by IIDEREM, V, REIF, R

“…We report for the first time the selective deposition of titanium silicide using a very low pressure chemical vapor deposition technique with silane and…”
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M2M: Challenges and opportunities by Ilderem, V.

“…Summary form only given. Embedded market is growing at a very fast pace encompassing many different market segments such as health, home, industrial, smart…”
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Embedded market: challenges and opportunities by Ilderem, Vida

“…There is a convergence trend in the computing, communication and consumer markets and with a forecast of an additional 1 billion connected computing users by…”
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Effect of boron on gate oxide degradation and reliability in PMOS devices by Brozek, Tomasz, Kyono, Carl, Ilderem, Vida

“…Modern CMOS technology widely utilizes dual poly gate technology to create surface channel PMOS devices with low threshold voltage. The paper presents analysis…”
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A 0.8-mu m advanced single-poly BiCMOS technology for high-densityand high-performance applications by Iranmanesh, A A, Ilderem, V, Biswal, M, Bastani, B

“…A single-poly, 0.8-mum advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process…”
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A cost-effective 0.25 /spl mu/m L/sub eff/ BiCMOS technology featuring graded-channel CMOS (GCMOS) and a quasi-self-aligned (QSA) NPN for RF wireless applications by Chai, F.K., Kyono, C., Ilderem, V., Kaneshiro, M., Zupac, D., Bigelow, S., Ramiah, C., Dahl, P., Braithwaite, R., Morgan, D., Hildreth, S., Grynkewich, G.

“…A cost-effective 0.25 /spl mu/m L/sub eff/ graded-channel BiCMOS technology is reported. GCMOS devices offer superior transconductance and short-channel…”
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Comprehensive study of substrate noise isolation for mixed-signal circuits by To, K.H., Welch, P., Bharatan, S., Lehning, H., Huynh, T.L., Thoma, R., Monk, D., Huang, W.A., Ilderem, V.

“…In this paper, we present a study on signal isolation approaches for mixed-signal circuits, via both simple test structures and actual circuits. Analysis was…”
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A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications by Iranmanesh, A.A., Ilderem, V., Biswal, M., Bastani, B.

“…A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process…”
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Low pressure chemical vapor deposition of titanium silicide by TEDROW, P. K, IIDEREM, V, REIF, R

“…The low pressure chemical vapor deposition (LPCVD) of titanium silicide is reported here for the first time. X-ray diffraction spectra show that the…”
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Minimizing body instability in deep sub-micron SOI MOSFETs for sub-1 V RF applications by Tseng, Y.-C., Huang, W.M., Mendicino, M., Welch, P., Ilderem, V., Woo, J.C.S.

“…We report an extensive study on the SOI body instability and the noise constraint dependence on device scaling for sub-1 V RF SOI CMOS applications. Also, the…”
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A low voltage graded-channel MOSFET (LV-GCMOS) for sub 1-volt microcontroller application by John, J.P., Ilderem, V., Changhae Park, Teplik, J., Klein, K., Cheng, S.

“…We report for the first time, a bulk silicon, low voltage graded-channel MOSFET (LV-GCMOS) capable of operating below 1 volt, while delivering the required…”
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0.6 μm, single poly advanced BiCMOS (ABiC IV) technology for ASIC applications by Iranmanesh, A., Ilderem, V., Solheim, A., Blair, C., Lam, L., Haas, F., Leibiger, S., Bouknight, L., Lahri, R., Biswal, M., Bastani, B.

“…An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The…”
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Process-Induced Charge Damage in PETEOS for Interlevel Dielectric Applications by Denton, H., Grynkewich, G., Ilderem, V., Lin, F., Parris, P., Shin, H.C.

“…This paper reports on the process characterization and optimization to reduce process-induced damage by PETEOS deposition used for interlevel dielectric…”
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An advanced 0.4 mu m BiCMOS technology for high performance ASIC applications by Kirchgessner, J., Teplik, J., Ilderem, V., Morgan, D., Parmar, R., Wilson, S.R., Freeman, J., Tracy, C., Cosentino, S.

“…An advanced 0.4 mu m BiCMOS technology has been developed for high-performance ASIC (application-specific integrated circuit) applications. The technology…”
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Submicron BiCMOS technologies for supercomputer and high speed system implementation by Bastani, B., Biswal, M., Iranmanesh, A., Lage, C., Bouknight, L., Ilderem, V., Solheim, A., Burger, W., Lahri, R., Small, J.

“…Submicron process technologies that allow a full implementation of CPU, first-level cache, second-level cache, and the main memory in the BiCMOS approach are…”
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A 0.8 mu m advanced single poly BiCMOS technology for high density and high performance applications by Ilderem, V., Iranmanesh, A., Solheim, A., Lam, L., Blair, C., Lahri, R., Leibiger, S., Bouknight, L., Biswal, M., Bastani, B.

“…A single poly, 0.8 mu m BiCMOS technology having both high-performance CMOS and 14 GHz ASPECT III n-p-n transistors is described. The advanced features of this…”
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Device design methodology to optimize low-frequency noise in advanced SOI CMOS technology for RF ICs by Ying-Che Tseng, Huang, W.M., Mendiciono, M., Ngo, D., Ilderem, V., Woo, J.C.S.

“…This paper reports on a comprehensive study of low-frequency (LF) noise in surface-channel dual-poly SOI CMOS-FETs. A new understanding of the pre-kink and…”
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Advanced single poly BiCMOS technology for high performance programmable TTL/ECL applications by Iranmanesh, A., Jurichich, S., Ilderem, V., Jerome, R., Joshi, S.P., Biswal, M., Bastani, B.

“…An optimized process has been developed by integration of several high-performance device modules such as PtSi Schottky barrier diodes, lateral p-n-p…”
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Application of lightly doped buried-layer for the reduction of the interconnection and junction capacitances by Iranmanesh, A., Jerome, R., Solheim, A., Ilderem, V., Dadgar, A., Bouknight, L., Biswal, M., Batani, B.

“…Interconnection delay plays a dominant role in determining the speed performance of todays integrated circuits. It is shown that the formation of a lightly…”
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