Search Results - "Ikehashi, T."

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  1. 1

    Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory by Ikehashi, T., Imamiya, K., Sakui, K.

    “…With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin…”
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    Journal Article
  2. 2
  3. 3

    A high power-handling RF MEMS tunable capacitor using quadruple series capacitor structure by Yamazaki, H., Ikehashi, T., Saito, T., Ogawa, E., Masunaga, T., Ohguro, T., Sugizaki, Y., Shibata, H.

    “…This paper presents an RF MEMS tunable capacitor that achieves excellent power-handling property with relatively low actuation voltage. The tunable capacitor…”
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    Conference Proceeding
  4. 4

    A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's by Ohsawa, T., Higashi, T., Fujita, K., Ikehashi, T., Kajiyama, T., Fukuzumi, Y., Shino, T., Yamada, H., Nakajima, H., Minami, Y., Yamada, T., Inoh, K., Hamamoto, T.

    “…A 288 Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 /spl mu/m/sup 2/(7F/sup 2/ with F=0.175 /spl mu/m) which we named the…”
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    Conference Proceeding
  5. 5

    A Robust RF MEMS Variable Capacitor with Piezoelectric and Electrostatic Actuation by Ikehashi, T., Ohguro, T., Ogawa, E., Yamazaki, H., Kojima, K., Matsuo, M., Ishimaru, K., Ishiuchi, H.

    “…An RF MEMS variable capacitor using hybrid actuation of piezoelectric and electrostatic forces is presented. A surface micromachining process is used to…”
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    Conference Proceeding
  6. 6

    A 125-mm(2) 1-Gb NAND flash memory with 10-MByte/s program speed by Imamiya, K, Nakamura, H, Himeno, T, Yarnamura, T, Ikehashi, T, Takeuchi, K, Kanda, K, Hosono, K, Futatsuyama, T, Kawai, K, Shirota, R, Arai, N, Arai, F, Hatakeyama, K, Hazama, H, Saito, M, Meguro, H, Conley, K, Quader, K

    Published in IEEE journal of solid-state circuits (01-11-2002)
    “…A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-mum CMOS STI technology. The effective cell…”
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    Journal Article
  7. 7

    An ESD preotection device using normally-on MEMS switch by Ikehashi, T., Saito, T.

    “…We investigate normally-off and normally-on MEMS switches as ESD protection devices. The normally-on type switch behaves as an ESD protection only when the…”
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    Conference Proceeding
  8. 8

    A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed by Imamiya, K., Nakamura, H., Himeno, T., Yarnamura, T., Ikehashi, T., Takeuchi, K., Kanda, K., Hosono, K., Futatsuyama, T., Kawai, K., Shirota, R., Arai, N., Arai, F., Hatakeyama, K., Hazama, H., Saito, M., Meguro, H., Conley, K., Quader, K., Chen, J.J.

    Published in IEEE journal of solid-state circuits (01-11-2002)
    “…A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-/spl mu/m CMOS STI technology. The effective…”
    Get full text
    Journal Article
  9. 9

    A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed by Imamiya, K, Nakamura, H, Himeno, T, Yarnamura, T, Ikehashi, T, Takeuchi, K, Kanda, K, Hosono, K, Futatsuyama, T, Kawai, K, Shirota, R, Arai, N, Arai, F, Hatakeyama, K, Hazama, H, Saito, M, Meguro, H, Conley, K, Quader, K, Chen, J.J

    Published in IEEE journal of solid-state circuits (01-11-2002)
    “…[...] the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized…”
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    Journal Article
  10. 10

    A 125-mm super(2) 1-Gb NAND flash memory with 10-MByte/s program speed by Imamiya, K, Nakamura, H, Himeno, T, Yarnamura, T, Ikehashi, T, Takeuchi, K, Kanda, K, Hosono, K, Futatsuyama, T, Kawai, K, Shirota, R, Arai, N, Arai, F, Hatakeyama, K, Hazama, H, Saito, M, Meguro, H, Conley, K, Quader, K, Chen, J J

    Published in IEEE journal of solid-state circuits (01-01-2002)
    “…A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13- mu m CMOS STI technology. The effective…”
    Get full text
    Journal Article
  11. 11

    A 130-mm(2), 256-Mbit NAND flash with shallow trenchisolation technology by Imamiya, K, Sugiura, Y, Nakamura, H, Himeno, T, Takeuchi, K, Ikehashi, T, Kanda, K, Hosono, K, Shirota, R, Aritome, S, Shimizu, K, Hatakeyama, K, Sakui, K

    Published in IEEE journal of solid-state circuits (01-11-1999)
    “…A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 mum is…”
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    Journal Article
  12. 12

    A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology by Imamiya, K., Sugiura, Y., Nakamura, H., Himeno, T., Takeuchi, K., Ikehashi, T., Kanda, K., Hosono, K., Shirota, R., Aritome, S., Shimizu, K., Hatakeyama, K., Sakui, K.

    Published in IEEE journal of solid-state circuits (01-11-1999)
    “…A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 /spl mu/m…”
    Get full text
    Journal Article
  13. 13

    The low-energy theorem of pion photoproduction using the Skyrme model by Ikehashi, Tamio, Ohta, Koichi

    Published in Nuclear physics. A (02-10-1995)
    “…We reassess the validity of the current-algebra based low-energy theorem of pion photoproduction on the nucleon using the Skyrme model. We find that one of the…”
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    Journal Article
  14. 14

    130-mm super(2), 256-Mbit NAND flash with shallow trench isolation technology by Imamiya, Kenichi, Sugiura, Yoshihisa, Nakamura, Hiroshi, Himeno, Toshihiko, Takeuchi, Ken, Ikehashi, Tamio, Kanda, Kazushige, Hosono, Koji, Shirota, Riichiro, Aritome, Seiichi, Shimizu, Kazuhiro, Hatakeyama, Kazuo, Sakui, Koji

    Published in IEEE journal of solid-state circuits (01-11-1999)
    “…A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 mu m is…”
    Get full text
    Journal Article
  15. 15

    A CMOS embedded RF-MEMS tunable capacitor for multi-band/multi-mode smartphones by Kurui, Y., Yamazaki, H., Shimooka, Y., Saito, T., Ogawa, E., Ogawa, T., Ikehashi, T., Sugizaki, Y., Shibata, H.

    “…This paper reports on 1-chip RF-MEMS tunable capacitor that equips CMOS driver circuit in the underlying layer. A Wafer Level Chip Scale Package (WLCSP)…”
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    Conference Proceeding
  16. 16

    A 3V Operation RF MEMS Variable Capacitor using Piezoelectric and Electrostatic Actuation with Lithographical Bending Control by Ikehashi, T., Ogawa, E., Yamazaki, H., Ohguro, T.

    “…A 3 V operation RF MEMS variable capacitor using hybrid actuation of piezoelectric and electrostatic forces is presented. Bending of the piezoelectric actuator…”
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    Conference Proceeding
  17. 17

    A long-term reliability analysis of a creep-immune RF-MEMS tunable capacitor by Ogawa, E., Masunishi, K., Ikehashi, T., Saito, T., Yamazaki, H., Tomizawa, Y., Sugizaki, Y.

    “…Actuators used in RF-MEMS tunable capacitors have an issue of creep-induced deformation. The creep is caused by a ductile-metal beam which is indispensable to…”
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    Conference Proceeding
  18. 18

    Low profile double resonance frequency tunable antenna using RF MEMS variable capacitor for digital terrestrial broadcasting reception by Tsutsumi, Y., Nishio, M., Obayashi, S., Shoki, H., Ikehashi, T., Yamazaki, H., Ogawa, E., Saito, T., Ohguro, T., Morooka, T.

    “…It is difficult to realize the built-in antenna for wideband systems, because a frequency bandwidth of the low profile antenna is narrow. A frequency tunable…”
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    Conference Proceeding
  19. 19
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    Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND memory by Ikehashi, T., Imamiya, K., Sakui, K.

    “…With the use of a device simulator, we show that an ESD protection circuit whose junction is filled with contacts is suited to a scaled STI process with thin…”
    Get full text
    Conference Proceeding