Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage

A dual-loop architecture employs eight distributed microregulators (UREGs) to achieve load response times below 500 ps in 45-nm SOI CMOS. The trip point of an asynchronous comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from a slow...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 47; no. 4; pp. 863 - 874
Main Authors:	Bulzacchelli, J. F., Toprak-Deniz, Z., Rasmus, T. M., Iadanza, J. A., Bucossi, W. L., Seongwon Kim, Blanco, R., Cox, C. E., Chhabra, M., LeBlanc, C. D., Trudeau, C. L., Friedman, D. J.
Format:	Journal Article Conference Proceeding
Language:	English
Published:	New York, NY IEEE 01-04-2012 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Applied sciences Bang-bang control Charge pumps Circuit properties Circuits of signal characteristics conditioning (including delay circuits) CMOS CMOS delay line CMOS integrated circuits Control systems Control theory Design. Technologies. Operation analysis. Testing Direct current distributed regulator Electric potential Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Feedback loop Integrated circuits Inverters linear regulator load response time load sharing low-dropout regulator Regulators Response time ripple reduction Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors Time factors Voltage Voltage control Load distribution High precision Jitter Feedback regulation Clock Linear control distributed regulator Silicon on insulator technology Feedback Complementary MOS technology CMOS delay line Comparator circuit Charge pumping load sharing PMOS technology low-dropout regulator Resource sharing Calibration Distributed system Switching load response time Bang-bang control Response time Slew rate ripple reduction Delay line Linear regulator On off effect
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Summary:	A dual-loop architecture employs eight distributed microregulators (UREGs) to achieve load response times below 500 ps in 45-nm SOI CMOS. The trip point of an asynchronous comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from a slow outer feedback loop. The feedback through the charge pumps also ensures balanced load sharing among the UREGs. Two techniques are introduced to reduce the output ripple generated by switching the pMOS passgate on and off: hybrid fast/slow passgate control (in which the DC portion of the load current is supplied by a parallel output device with slew-rate-limited gate drive) and pMOS strength calibration (which adjusts the active width of the passgate to compensate for PVT variations). The distributed regulator system is integrated into a DDR3 I/O core and supplies power to CMOS delay lines used for clock-to-data deskewing. Each of the eight UREGs is sized to provide up to 5.3 mA of load current and occupies an area of 55 × 60 μm 2 . The measured DC load regulation is better than 10 mV down to an 85-mV dropout voltage. Jitter readings of the CMOS delay lines indicate output noise close to 28 mVpp.
Bibliography:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2012.2185354