Search Results - "ISHIUCHI, Hidemi"

An intelligent bipolar actuation method with high stiction immunity for RF MEMS capacitive switches and variable capacitors by Yamazaki, Hiroaki, Ikehashi, Tamio, Ohguro, Tatsuya, Ogawa, Etsuji, Kojima, Kenji, Ishimaru, Kazunari, Ishiuchi, Hidemi

“…We propose an intelligent bipolar actuation (IBA) method for electrostatic actuators, which can suppress stiction induced by dielectric charging. The high…”
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Brownian Motion of a Kink in Sine-Gordon System and Diffusion Constant by Wada, Yasushi, Ishiuchi, Hidemi

“…In a one-dimensional sine-Gordon system, a propagating vibration with small amplitude collides with a kink to produce a translation of the kink, giving rise to…”
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Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Hu, C., Liu, T.-J.K.

“…Forward body biasing is a promising approach for realizing optimum threshold-voltage ( V TH ) scaling in the era when gate dielectric thickness can no longer…”
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MOSFET design for forward body biasing scheme by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Tsu-Jae King Liu, Chenming Hu

“…Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body…”
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MOSFET hot-carrier reliability improvement by forward-body bias by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Chenming Hu, Tsu-Jae King Liu

“…Active threshold voltage V/sub TH/ control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and…”
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Executive Summary by Wilson, Linda, Ishiuchi, Hidemi, Gargini, Paolo, Allan, Alan, Balestra, Francis, Hayashi, Yoshihiro, Kenny, Leo

“…The events of 2020 and 2021 were very dramatic as the whole world was overwhelmed by the first pandemic in 100 years. However, the need to remotely…”
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Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate by Momose, H.S., Ohguro, T., Nakamura, S.-I., Toyoshima, Y., Ishiuchi, H., Iwai, H.

“…The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a [111] surface-oriented Si…”
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High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide by Inaba, S., Okano, K., Matsuda, S., Fujiwara, M., Hokazono, A., Adachi, K., Ohuchi, K., Suto, H., Fukui, H., Shimizu, T., Mori, S., Oguma, H., Murakoshi, A., Itani, T., Iinuma, T., Kudo, T., Shibata, H., Taniguchi, S., Takayanagi, M., Azuma, A., Oyamatsu, H., Suguro, K., Katsumata, Y., Toyoshima, Y., Ishiuchi, H.

“…The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance…”
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Modeling of Electron Mobility Degradation for HfSiON MISFETs by Tanimoto, Hiroyoshi, Kondo, Masaki, Enda, Toshiyuki, Aoki, Nobutoshi, Iijima, Ryosuke, Watanabe, Takeshi, Takayanagi, Mariko, Ishiuchi, Hidemi

“…The electron mobility degradation for HfSiON MISFETs was investigated. We found that the degradation had two origins; one is Coulomb scattering caused by fixed…”
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Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology by Inaba, S., Nagano, H., Miyano, K., Mizushima, I., Okayama, Y., Nakauchi, T., Ishimaru, K., Ishiuchi, H.

“…In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) is investigated with a view to realizing high-speed and low-power CMOS…”
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Lithography by Neisser, Mark, Levinson, Harry J., Wurm, Stefan, Kyser, David, Watanabe, Takeo, Macwilliams, Ken, Ishiuchi, Hidemi, Trybula, Walt, Hayashi, Naoya, Fedynyshyn, Ted, Higgins, Craig, Nakamura, Tsuyoshi, Resnick, Doug, Preil, Moshe, Lercel, Michael, Aoyama, Hajime, Hosler, Erik

“…Historically, improvements in lithography have enabled improved chip technologies. The International Roadmap for Devices and Systems (IRDS) Lithography roadmap…”
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SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology by Inaba, S., Miyano, K., Nagano, H., Hokazono, A., Ohuchi, K., Mizushima, I., Oyamatsu, H., Tsunashima, Y., Ishimaru, K., Toyoshima, Y., Ishiuchi, H.

“…In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the…”
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Simulation of NOR-Flash Memory Cells Focusing on Narrow Channel Effects on VTH Dispersion by Kondo, M., Nakauchi, T., lto, S., Aoki, N., Nakamura, M., Naruke, K., Ishiuchi, H.

“…In this paper, we present novel simulation results including threshold voltage (V TH ) dispersions caused by process variations for highly scaled NOR-flash…”
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Impact of Hf concentration on performance and reliability for HfSiON-CMOSFET by Watanabe, T., Takayanagi, M., Kojima, K., Ishimaru, K., Ishiuchi, H., Sekine, K., Yamasaki, H., Eguchi, K.

“…65 nm gate length HfSiON-CMOSFET was fabricated with various Hf concentrations and gate spacers in view of device performance and reliability. The negative…”
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Hot-electron-induced minority-carrier generation in bipolar junction transistors by Ishiuchi, H., Tamba, N., Shott, J.D., Knorr, C.J., Wong, S.S.

“…The authors report on the observation and analysis of minority-carrier generation in the collector and the substrate of n-p-n bipolar junction transistors as a…”
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A highly manufacturable high density embedded SRAM technology for 90nm CMOS by FUKAURA, Yasuhiro, KASAI, Kunihiro, OKAYAMA, Yasunori, KAWASAKI, Hirohisa, ISOBE, Kazuaki, KANDA, Masahiko, ISHIMARU, Kazunari, ISHIUCHI, Hidemi

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An experimental 4-Mbit CMOS DRAM by Furuyama, T., Ohsawa, T., Watanabe, Y., Ishiuchi, H., Watanabe, T., Tanaka, T., Natori, K., Ozawa, O.

“…A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel…”
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Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's by Ishiuchi, H., Matsumoto, Y., Sawada, S., Ozawa, O.

“…Intrinsic capacitance of lightly doped drain (LDD) MOSFET's is measured by means of a four-terminal method without using any on-chip measurement circuits. The…”
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Analytical model for oblique ion reflection at the Si surface by Mizuno, T., Higuchi, T., Ishiuchi, H., Matsumoto, Y., Saitoh, Y., Sawada, S., Shinozaki, S.

“…Experimental and analytical studies on oblique ion implantation into a Si trench sidewall are discussed. The observation that implanted ions at small incident…”
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A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs by Furuyama, T., Ishiuchi, H., Tanaka, H., Watanabe, Y., Kohyama, Y., Kimura, T., Muraoka, K., Sugiura, S., Natori, K.

“…A latch-up-like failure phenomenon that shows hysteresis in the V/sub cc/-I/sub cc/ characteristics observed in a high-density CMOS dynamic RAM that utilizes…”
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