Search Results - "ISHIMARU, Kazunari"

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  1. 1

    Flash Memory and Its Manufacturing Technology for Sustainable World by Ishimaru, Kazunari, Fujiwara, Makoto, Miyagawa, Hidenori, Aiba, Yuta

    “…In today's data-driven society, memory is an unavoidable component. IoT and 5G are accelerating data generation exponentially, and the demands of high-capacity…”
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    Journal Article
  2. 2

    Analysis and Optimization of Defect Generation Due to Mechanical Stress in High-Density SRAM by Ishimaru, Kazunari, Tamura, Mizuki, Fujii, Osamu

    “…Static random-access memory (SRAM) is an essential component for realizing large-scale integration (LSI). The future transition to a 48 V DC supply in…”
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    Journal Article
  3. 3

    Guest Editorial Special Section on the Second Electron Devices Technology and Manufacturing (EDTM) Conference 2018 by Ishimaru, Kazunari, Horiguchi, Naoto, Nojiri, Kazuo, Zhang, Paul Lining, Berger, Paul R.

    “…Performance improvement by simple device scaling is running out of steam. Design and Technology Co-Optimization (DTCO) and System and Technology…”
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    Journal Article
  4. 4

    Challenges of Flash Memory for Next Decade by Ishimaru, Kazunari

    “…It was more than 50 years ago, the first floating gate MOS transistor was proposed and 30 years has passed after the first NAND flash memory was…”
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    Conference Proceeding
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    45nm/32nm CMOS – Challenge and perspective by Ishimaru, Kazunari

    Published in Solid-state electronics (01-09-2008)
    “…Production of 45nm node CMOS has already started. However, difficulty of new technology development is increasing and some company dropped off from the…”
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    Journal Article
  7. 7

    "Memory" for Sustainable Society by Ishimaru, Kazunari

    “…In today's advanced information society, the amount of data being generated is exploding, and within a few years, the annual amount of data generated is…”
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    Conference Proceeding
  8. 8

    Non-Volatile Memory Technology for Data Age by Ishimaru, Kazunari

    “…Now everything is connected and because of the data explosion, data generation per year will exceed 160ZB in 2025. Non-volatile memory is a key component…”
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    Conference Proceeding
  9. 9

    An intelligent bipolar actuation method with high stiction immunity for RF MEMS capacitive switches and variable capacitors by Yamazaki, Hiroaki, Ikehashi, Tamio, Ohguro, Tatsuya, Ogawa, Etsuji, Kojima, Kenji, Ishimaru, Kazunari, Ishiuchi, Hidemi

    Published in Sensors and actuators. A. Physical. (12-09-2007)
    “…We propose an intelligent bipolar actuation (IBA) method for electrostatic actuators, which can suppress stiction induced by dielectric charging. The high…”
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    Journal Article
  10. 10

    45nm/32nm CMOS ˜ Challenge and Perspective by Ishimaru, K.

    “…Product of 45 nm node technology will start by the end of this year. However, difficulty of new technology development is increasing and some company dropped…”
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    Conference Proceeding
  11. 11

    Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond by Inaba, S., Kawasaki, H., Okano, K., Izumida, T., Yagishita, A., Kaneko, A., Ishimaru, K., Aoki, N., Toyoshima, Y.

    “…V t variability in FinFET SRAM is evaluated for the first time by direct measurement of the cell transistors down to 25 nm gate length. By taking the V,…”
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    Conference Proceeding
  12. 12

    45nm/32nm CMOS ∼challenge and perspective by Ishimaru, K.

    “…Product of 45 nm node technology will start by the end of this year. However, difficulty of new technology development is increasing and some company dropped…”
    Get full text
    Conference Proceeding
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    Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Hu, C., Liu, T.-J.K.

    Published in IEEE transactions on electron devices (01-10-2008)
    “…Forward body biasing is a promising approach for realizing optimum threshold-voltage ( V TH ) scaling in the era when gate dielectric thickness can no longer…”
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    Journal Article
  15. 15

    SSCS WiC and EDS WiEDS Diversity Panel Luncheon: “How Does Diversity Impact Productivity in Your Organization?” [Society News] by Li, Pei-Wen, Menon, P. Susthitha, Ishimaru, Kazunari

    “…Provides society information that may include news, reviews or technical notes that should be of interest to practitioners and researchers…”
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    Journal Article
  16. 16

    MOSFET design for forward body biasing scheme by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Tsu-Jae King Liu, Chenming Hu

    Published in IEEE electron device letters (01-05-2006)
    “…Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body…”
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    Journal Article
  17. 17

    MOSFET hot-carrier reliability improvement by forward-body bias by Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Chenming Hu, Tsu-Jae King Liu

    Published in IEEE electron device letters (01-07-2006)
    “…Active threshold voltage V/sub TH/ control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and…”
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    Journal Article
  18. 18

    Evaluation of the junction delineation accuracy and reproducibility with the SSRM technique by Eyben, Pierre, Vanhaeren, Danielle, Janssens, Tom, Hantschel, Thomas, Vandervorst, Wilfried, Adachi, Kanna, Ishimaru, Kazunari

    Published in Microelectronic engineering (01-03-2007)
    “…Within this work, we have studied ultrathin n- and p-type extension implants in order to evaluate the junction delineation accuracy and reproducibility of the…”
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    Journal Article Conference Proceeding
  19. 19

    Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology by Inaba, S., Nagano, H., Miyano, K., Mizushima, I., Okayama, Y., Nakauchi, T., Ishimaru, K., Ishiuchi, H.

    Published in IEEE journal of solid-state circuits (01-06-2006)
    “…In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) is investigated with a view to realizing high-speed and low-power CMOS…”
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    Journal Article
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    SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology by Inaba, S., Miyano, K., Nagano, H., Hokazono, A., Ohuchi, K., Mizushima, I., Oyamatsu, H., Tsunashima, Y., Ishimaru, K., Toyoshima, Y., Ishiuchi, H.

    Published in IEEE transactions on electron devices (01-09-2004)
    “…In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the…”
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    Journal Article