Search Results - "IONICA, Irina"

A review of electrical characterization techniques for ultrathin FDSOI materials and devices by Cristoloveanu, Sorin, Bawedin, Maryline, Ionica, Irina

“…The characterization of nanosize SOI materials and devices is challenging because multiple oxides, interfaces and channels coexist. Conventional measurement…”
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Impact of Blend Morphology on Interface State Recombination in Bulk Heterojunction Organic Solar Cells by Bouthinon, Benjamin, Clerc, Raphaël, Vaillant, Jérôme, Verilhac, Jean-Marie, Faure-Vincent, Jérôme, Djurado, David, Ionica, Irina, Man, Gabriel, Gras, Antoine, Pananakakis, Georges, Gwoziecki, Romain, Kahn, Antoine

“…This work is a reinvestigation of the impact of blend morphology and thermal annealing on the electrical performance of regioregular‐P3HT:PC60BM bulk…”
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Optical Switching of Porphyrin-Coated Silicon Nanowire Field Effect Transistors by Winkelmann, Clemens B., Ionica, Irina, Chevalier, Xavier, Royal, Guy, Bucher, Christophe, Bouchiat, Vincent

“…We study porphyrin derivative coated silicon nanowire field effect transistors (SiNW-FETs), which display a large, stable, and reproducible conductance…”
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Effect of back gate on parasitic bipolar effect in FD SOI MOSFETs by Fanyu Liu, Ionica, Irina, Bawedin, Maryline, Cristoloveanu, Sorin

“…In short-channel fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs, the drain leakage current is enhanced by the parasitic bipolar transistor. The…”
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Super-Nernstian pH detection using out-of-equilibrium body potential in silicon on insulator ISFET sensors: Proof-of-concept and optimization paths by Alepidis, Miltiadis, Delacour, Cecile, Bawedin, Maryline, Ionica, Irina

“…In this work, we demonstrate pH sensing using the out-of-equilibrium body potential (VB) monitored in silicon-on-insulator (SOI) double-gate “ISFET-like”…”
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Novel DNA Biosensor Based on the Out-of-Equilibrium Body Potential Method in Silicon-on-Insulator by Benea, Licinius, Popescu, Melania, Bawedin, Maryline, Simion, Monica, Ionica, Irina

“…In this paper, we applied the out-of-equilibrium body potential measurements in a silicon-on-insulator (SOI) structure as a mean of DNA detection. The biochips…”
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Out-of-Equilibrium Body Potential Measurement on Silicon-on-Insulator With Deposited Metal Contacts by Alepidis, Miltiadis, Bouchard, Aude, Delacour, Cecile, Bawedin, Maryline, Ionica, Irina

“…This article focuses on one of the floating body effects in silicon-on-insulator (SOI) substrates, the out-of-equilibrium body potential. Unlike the already…”
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A simple test structure for the electrical characterization of front and back channels for advanced SOI technology development by Alepidis, M., Ionica, I., Milesi, F., Bresson, N., Gaudin, G., Cristoloveanu, S., Reboh, S.

“…•Double gate structures for channel material and gate stack characterization.•Easy and simple techniques based on the pseudo-MSOFET configuration.•Fast…”
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Out-of-equilibrium body potential measurements in pseudo-MOSFET for sensing applications by Benea, Licinius, Bawedin, Maryline, Delacour, Cécile, Ionica, Irina

“…•The aim of this paper is to present the out-of-equilibrium body potential behaviour in the Ψ-MOSFET configuration.•Consistent measurements in this…”
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Origin of the Out-of-Equilibrium Body Potential In Silicon on Insulator Devices With Metal Contacts by Alepidis, M., Ghibaudo, G., Bawedin, M., Ionica, I.

“…This work addresses the origin of the transient body potential variation in silicon on insulator (SOI) with deposited metal contacts, under back-gate bias…”
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Methodology for parameters extraction with undoped junctionless EZ-FETs by Zerhouni Abdou, N., Reboh, S., Brunet, L., Alepidis, M., Acosta Alba, P., Cristoloveanu, S., Ionica, I.

“…The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture…”
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Experimental and simulation investigation of the out-of-equilibrium phenomena on the pseudo-MOSFET configuration under transient linear voltage ramps by Alepidis, Miltiadis, Benea, Licinius, Bucci, Davide, Mescot, Xavier, Bawedin, Maryline, Ionica, Irina

“…The pseudo-MOSFET configuration is an electrical characterization technique developed for silicon-on-insulator (SOI) wafers. The wide variety of experiments…”
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Undoped junctionless EZ-FET: Model and measurements by Zerhouni Abdou, N., Reboh, S., Alepidis, M., Brunet, L., Acosta Alba, P., Cristoloveanu, S., Ionica, I.

“…•An EZFET is a simple and reliable characterization device for substrates and gate stacks.•Junctionless EZFET removes the temperature limitation of junctions…”
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Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs by Fanyu Liu, Ionica, Irina, Bawedin, Maryline, Cristoloveanu, Sorin

“…We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. The method is based…”
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Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration by Pirro, Luca, Diab, Amer, Ionica, Irina, Ghibaudo, Gerard, Faraone, Lorenzo, Cristoloveanu, Sorin

“…Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the…”
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Neuron‐Gated Silicon Nanowire Field Effect Transistors to Follow Single Spike Propagation within Neuronal Network by Delacour, Cécile, Veliev, Farida, Crozes, Thierry, Bres, Guillaume, Minet, Julien, Ionica, Irina, Ernst, Thomas, Briançon-Marjollet, Anne, Albrieux, Mireille, Villard, Catherine

“…Silicon nanowire field effect transistors (SiNW‐FETs) provide a local probe for sensing neuronal activity at the subcellular scale, thanks to their nanometer…”
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Back-gate effects and mobility characterization in junctionless transistor by Parihar, Mukta Singh, Liu, Fanyu, Navarro, Carlos, Barraud, Sylvain, Bawedin, Maryline, Ionica, Irina, Kranti, Abhinav, Cristoloveanu, Sorin

“…This work addresses the effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with…”
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RC Model for Frequency Dependence of Split C hbox - - V Measurements on Bare SOI Wafers by Diab, Amer, Ionica, Irina, Ghibaudo, Gerard, Cristoloveanu, Sorin

“…The feasibility of split C hbox - - V measurements for direct evaluation of carrier mobility in as-fabricated silicon-on-insulator wafers has been…”
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[Formula Omitted] Model for Frequency Dependence of Split [Formula Omitted] Measurements on Bare SOI Wafers by Diab, Amer, Ionica, Irina, Ghibaudo, Gerard, Cristoloveanu, Sorin

“…The feasibility of split [Formula Omitted] measurements for direct evaluation of carrier mobility in as-fabricated silicon-on-insulator wafers has been…”
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Low Temperature Junction Formation for EZ-FET by Zerhouni Abdou, N., Acosta Alba, P., Brunet, L., Milesi, F., Opprecht, M., Gallard, M., Reboh, S., Ionica, I.

“…The EZ-FET is a device with simplified architecture and processing that enables fast electrical characterization of semiconductor films on insulators (SOI)…”
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