Search Results - "ILGWEON KIM"
-
1
Roles of Residual Stress in Dynamic Refresh Failure of a Buried-Recessed-Channel-Array Transistor (B-CAT) in DRAM
Published in IEEE electron device letters (01-07-2016)“…We clarify the role of metal gates (e.g., TiN) on the degradation of the state-of-the-art buried-channel-array transistor (B-CAT) in dynamic random access…”
Get full text
Journal Article -
2
Study on off-state hot carrier degradation and recovery of NMOSFET in SWD circuits of DRAM
Published in 2016 IEEE International Integrated Reliability Workshop (IIRW) (2016)“…We investigated threshold voltage degradation and recovery of short channel NMOS transistors in the sub wordline driver (SWD), where the source of NMOS…”
Get full text
Conference Proceeding -
3
Characteristics of p-channel Si nano-crystal memory
Published in IEEE transactions on electron devices (01-05-2001)“…In this work, the feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. By comparing the programming…”
Get full text
Journal Article -
4
Room temperature single electron effects in a Si nano-crystal memory
Published in IEEE electron device letters (01-12-1999)“…An MOS memory based on Si nano-crystals has been fabricated. We have developed a repeatable process of forming uniform, small-size and high-density Si…”
Get full text
Journal Article -
5
Impact of Drain Induced Barrier Lowering on Read Scheme in Silicon Nanocrystal Memory with Two-Bit-per-Cell Operation
Published in Japanese Journal of Applied Physics (01-02-2006)Get full text
Journal Article -
6
Programming characteristics of p-channel Si nano-crystal memory
Published in IEEE electron device letters (01-06-2000)“…In this work, the programming characteristics of a p-channel nano-crystal memory is studied. The hole tunneling component from the inversion layer and the…”
Get full text
Journal Article -
7
Si Nanocrystal Memory Cell with Room-Temperature Single Electron Effects
Published in Japanese Journal of Applied Physics (01-02-2001)“…A metal oxide semiconductor (MOS) memory based on Si nanocrystals has been fabricated. We have developed a repeatable process for forming uniform, small and…”
Get full text
Journal Article -
8
Effect of Back Gate on Word Line Disturb Immunity of a Vertical Channel DRAM Cell Array Transistor
Published in 2024 IEEE International Reliability Physics Symposium (IRPS) (14-04-2024)“…A novel vertical channel DRAM cell array transistor has been proposed and verified. A back gate shared by adjacent two word lines has been introduced to have…”
Get full text
Conference Proceeding -
9
Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era
Published in ESSDERC 2007 - 37th European Solid State Device Research Conference (01-09-2007)“…A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data…”
Get full text
Conference Proceeding
-
10
FN-degradation of S-RCAT with different grain size and oxidation method
Published in Microelectronic engineering (01-05-2014)“…•We realized Sphere-shaped-recess-cell-array-transistor to improve short channel effect.•Negative shift of threshold voltage and increase of swing were…”
Get full text
Journal Article -
11
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process
Published in 2018 IEEE Symposium on VLSI Circuits (01-06-2018)“…A sub-0.85V, 6.4Gb/s TX-interleaved transceiver with fast wake-up time using 2-step charging control and a V OH calibration scheme is implemented using 20nm…”
Get full text
Conference Proceeding -
12
Off-state degradation with ac bias in PMOSFET
Published in Microelectronics and reliability (01-10-2016)“…For the first time, the current failure of p-channel MOSFETs used for the sub-wordline driver of state-of-the-art DRAM chips was investigated during off-state…”
Get full text
Journal Article -
13
-
14
Impact of Contact Resistance Reduction By Plasma Induced Damage Removal on Cold Temperature Characteristics of PMOSFETs and Inverter Circuits
Published in 2020 International Conference on Electronics, Information, and Communication (ICEIC) (01-01-2020)“…In this work we have investigated the impact of contact resistance reduction on cold temperature characteristics of MOSFETs. We used a simple in-situ Si soft…”
Get full text
Conference Proceeding -
15
Characteristics of P-channel Si nano-crystal memory
Published in Proceedings of IEEE. IEEE Region 10 Conference. TENCON 99. 'Multimedia Technology for Asia-Pacific Information Infrastructure' (Cat. No.99CH37030) (1999)“…The nano-crystal memory operates at low voltage compared to conventional flash memory due to thinner tunneling dielectrics, since the spacing between the Si…”
Get full text
Conference Proceeding -
16
Comparison of the characteristics of tunneling oxide and tunneling ON for p-channel nano-crystal memory
Published in ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) (1999)“…The nano-crystal memory operates at low voltage compared to conventional flash memory due to thinner tunneling dielectrics since the spacing between the Si…”
Get full text
Conference Proceeding -
17
The p-channel Si nano-crystal memory
Published in 2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) (2001)“…The feasibility of p-channel nano-crystal memory is demonstrated. The programming mechanism of p-channel nano-crystal memory was investigated by charge…”
Get full text
Conference Proceeding -
18
A silicon quantum wire transistor with one-dimensional subband effects
Published in Solid-state electronics (01-12-2000)“…A silicon quantum wire transistor, in which electrons are transported through a very narrow wire, has been fabricated using silicon-on-insulator technology,…”
Get full text
Journal Article -
19
Fabrication Of Silicon Quantum Dots On Oxide And Nitride
Published in Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135) (1998)“…One of the main approaches to nano-crystal non-volatile memory operating at room temperature is to reduce Si quantum dot size and increase density [1]. In this…”
Get full text
Conference Proceeding -
20
Quantized Conductance Of A Gate-All-Around Silicon Quantum Wire Transistor
Published in Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135) (1998)“…As the dimension of VLSI technology approaches the nanometer scale, various fabrication methods have been proposed to establish one-dimensional (1-D) electron…”
Get full text
Conference Proceeding