Search Results - "IEEE journal of solid-state circuits"

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks by Yu-Hsin Chen, Krishna, Tushar, Emer, Joel S., Sze, Vivienne

“…Eyeriss is an accelerator for state-of-the-art deep convolutional neural networks (CNNs). It optimizes for the energy efficiency of the entire system,…”
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XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks by Yin, Shihui, Jiang, Zhewei, Seo, Jae-Sun, Seok, Mingoo

“…We present XNOR-SRAM, a mixed-signal in-memory computing (IMC) SRAM macro that computes ternary-XNOR-and-accumulate (XAC) operations in binary/ternary deep…”
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A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications by Sadhu, Bodhisatwa, Tousi, Yahya, Hallin, Joakim, Sahl, Stefan, Reynolds, Scott K., Renstrom, Orjan, Sjogren, Kristoffer, Haapalahti, Olov, Mazor, Nadav, Bokinge, Bo, Weibull, Gustaf, Bengtsson, Hakan, Carlinger, Anders, Westesson, Eric, Thillberg, Jan-Erik, Rexberg, Leonard, Yeck, Mark, Xiaoxiong Gu, Ferriss, Mark, Duixian Liu, Friedman, Daniel, Valdes-Garcia, Alberto

“…This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and…”
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C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism by Jiang, Zhewei, Yin, Shihui, Seo, Jae-Sun, Seok, Mingoo

“…This article presents C3SRAM, an in-memory-computing SRAM macro. The macro is an SRAM module with the circuits embedded in bitcells and peripherals to perform…”
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A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a [Formula Omitted] Beamformer Flip-Chip Unit Cell by Kibaroglu, Kerim, Sayginer, Mustafa, Rebeiz, Gabriel M

“…This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel ([Formula…”
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CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks by Biswas, Avishek, Chandrakasan, Anantha P.

“…This paper presents an energy-efficient static random access memory (SRAM) with embedded dot-product computation capability, for binary-weight convolutional…”
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Cryo-CMOS Circuits and Systems for Quantum Computing Applications by Patra, Bishnu, Incandela, Rosario M., van Dijk, Jeroen P. G., Homulle, Harald A. R., Lin Song, Shahmohammadi, Mina, Staszewski, Robert Bogdan, Vladimirescu, Andrei, Babaie, Masoud, Sebastiano, Fabio, Charbon, Edoardo

“…A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout…”
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In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array by Jintao Zhang, Zhuo Wang, Verma, Naveen

“…This paper presents a machine-learning classifier where computations are performed in a standard 6T SRAM array, which stores the machine-learning model…”
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A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute by Valavi, Hossein, Ramadge, Peter J., Nestler, Eric, Verma, Naveen

“…Large-scale matrix-vector multiplications, which dominate in deep neural networks (DNNs), are limited by data movement in modern VLSI technologies. This paper…”
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UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision by Lee, Jinmook, Kim, Changhyeon, Kang, Sanghoon, Shin, Dongjoo, Kim, Sangyeob, Yoo, Hoi-Jun

“…An energy-efficient deep neural network (DNN) accelerator, unified neural processing unit (UNPU), is proposed for mobile deep learning applications. The UNPU…”
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A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS by SungWon Chung, Abediasl, Hooman, Hashemi, Hossein

“…A large-scale monolithic silicon nanophotonic phased array on a chip creates and dynamically steers a high-resolution optical beam in free space, enabling…”
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A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS by Wang, Yun, Wu, Rui, Pang, Jian, You, Dongwon, Fadila, Ashbir Aviat, Saengchan, Rattanan, Fu, Xi, Matsumoto, Daiki, Nakamura, Takeshi, Kubozoe, Ryo, Kawabuchi, Masaru, Liu, Bangan, Zhang, Haosheng, Qiu, Junjun, Liu, Hanli, Oshima, Naoki, Motoi, Keiichi, Hori, Shinichi, Kunihiro, Kazuaki, Kaneko, Tomoya, Shirane, Atsushi, Okada, Kenichi

“…This article presents the first 39-GHz phased-array transceiver (TRX) chipset for fifth-generation new radio (5G NR). The proposed transceiver chipset consists…”
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A Nonuniform Sparse 2-D Large-FOV Optical Phased Array With a Low-Power PWM Drive by Fatemi, Reza, Khachaturian, Aroutin, Hajimiri, Ali

“…Integrated optical phased arrays (OPAs) capable of adaptive beamforming and beam steering enable a wide range of applications. For many of these applications,…”
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An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier by Tang, Xiyuan, Shen, Linxiao, Kasap, Begum, Yang, Xiangxing, Shi, Wei, Mukherjee, Abhishek, Pan, David Z., Sun, Nan

“…This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor;…”
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An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver by Lee, Sangyeop, Hara, Shinsuke, Yoshida, Takeshi, Amakawa, Shuhei, Dong, Ruibing, Kasamatsu, Akifumi, Sato, Junji, Fujishima, Minoru

“…A single-chip CMOS transceiver (TRX) capable of wireless data rates up to 80 Gb/s using part of frequencies (252-279 GHz) covered by IEEE Std 802.15.3d is…”
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A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing by Jia, Hongyang, Valavi, Hossein, Tang, Yinqi, Zhang, Jintao, Verma, Naveen

“…In-memory computing (IMC) addresses the cost of accessing data from memory in a manner that introduces a tradeoff between energy/throughput and computation…”
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A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics/CMOS 3D-Integration Platform by Kim, Taehwan, Ngai, Tat, Timalsina, Yukta, Watts, Michael R., Stojanovic, Vladimir, Bhargava, Pavan, Poulton, Christopher V., Notaros, Jelena, Yaacobi, Ami, Timurdogan, Erman, Baiocco, Christopher, Fahrenkopf, Nicholas, Kruger, Seth

“…With the growing demand for automotive LiDAR and the maturation of silicon photonics platforms, optical phased arrays (OPAs) have emerged as a key technology…”
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A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors by Si, Xin, Liu, Rui, Yu, Shimeng, Liu, Ren-Shuo, Hsieh, Chih-Cheng, Tang, Kea-Tiong, Li, Qiang, Chang, Meng-Fan, Chen, Jia-Jing, Tu, Yung-Ning, Huang, Wei-Hsing, Wang, Jing-Hong, Chiu, Yen-Cheng, Wei, Wei-Chen, Wu, Ssu-Yen, Sun, Xiaoyu

“…Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence…”
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A Reconfigurable 3-D-Stacked SPAD Imager With In-Pixel Histogramming for Flash LIDAR or High-Speed Time-of-Flight Imaging by Hutchings, Sam W., Johnston, Nick, Gyongy, Istvan, Al Abbas, Tarek, Dutton, Neale A. W., Tyler, Max, Chan, Susan, Leach, Jonathan, Henderson, Robert K.

“…A 256 × 256 single-photon avalanche diode (SPAD) sensor integrated into a 3-D-stacked 90-nm 1P4M/40-nm 1P8M process is reported for flash light detection and…”
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A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio by Pang, Jian, Wu, Rui, Wang, Yun, Dome, Masato, Kato, Hisashi, Huang, Hongye, Tharayil Narayanan, Aravind, Liu, Hanli, Liu, Bangan, Nakamura, Takeshi, Fujimura, Takuya, Kawabuchi, Masaru, Kubozoe, Ryo, Miura, Tsuyoshi, Matsumoto, Daiki, Li, Zheng, Oshima, Naoki, Motoi, Keiichi, Hori, Shinichi, Kunihiro, Kazuaki, Kaneko, Tomoya, Shirane, Atsushi, Okada, Kenichi

“…This paper presents a 28-GHz CMOS four-element phased-array transceiver chip for the fifth-generation mobile network (5G) new radio (NR). The proposed…”
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