Search Results - "IEEE Proceedings of the Custom Integrated Circuits Conference"

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  1. 1

    Stochastic testing simulator for integrated circuits and MEMS: Hierarchical and sparse techniques by Zheng Zhang, Xiu Yang, Marucci, Giovanni, Maffezzoni, Paolo, Elfadel, Ibrahim Abe M., Karniadakis, George, Daniel, Luca

    “…Process variations are a major concern in today's chip design since they can significantly degrade chip performance. To predict such degradation, existing…”
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    Conference Proceeding
  2. 2

    True Random Number Generator circuits based on single- and multi-phase beat frequency detection by Qianying Tang, Bongjin Kim, Yingjie Lao, Parhi, Keshab K., Kim, Chris H.

    “…A fully-digital True Random Number Generator (TRNG) measures the frequency difference between two free-running ring oscillators, or in other words the beat…”
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    Conference Proceeding
  3. 3

    Impact of random telegraph noise on CMOS logic circuit reliability by Matsumoto, Takashi, Kobayashi, Kazutoshi, Onodera, Hidetoshi

    “…The leading edge products have a feature size of 22 nm in 2014. Designing reliable systems has become a big challenge in recent years. Transistor reliability…”
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    Conference Proceeding
  4. 4

    A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals by Bongjin Kim, Kundu, Somnath, Ko, Seokkyun, Kim, Chris H.

    “…A VCO-based ADC featuring a multi-phase beat frequency based quantization scheme with first order noise shaping is demonstrated in a 65nm CMOS process. The…”
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    Conference Proceeding
  5. 5

    A 0.8V 140nW low-noise energy harvesting CMOS APS imager with fully digital readout by Cevik, Ismail, Ay, Suat U.

    “…This paper presents a novel CMOS active pixel sensor (APS) imager with fully digital global readout channel and continuous time on-chip energy harvesting…”
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    Conference Proceeding
  6. 6

    Directions in future of SRAM with QDR-WideIO for high performance networking applications and beyond by Keshavarzi, Ali, Maheshwari, Dinesh, Mattos, Derwin, Kapre, Ravi, Krishnegowda, Sandeep, Whately, Morgan, Gopalswamy, Sudhir

    “…In this paper we describe the high performance synchronous QDR-WideIO SRAM KGD from Cypress that is architected with fast and wide interface with optimized…”
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    Conference Proceeding
  7. 7

    Advanced modeling and simulation of state-of-the-art high-speed I/O interfaces by Jaeha Kim

    “…Today's high-speed I/O interfaces demand extensive modeling and simulation to: design optimal equalization to compensate channel loss, compare different…”
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  8. 8

    Virtual de-embedding study for the accurate extraction of Fin FET gate resistance by Warnock, Shireen, Groves, Rob, Hongmei Li, Wachnik, Richard, Kotecha, Pooja, Sungjae Lee, Ning Lu, Solomon, Paul, Jenkins, Keith

    “…Accurate measurement of FET gate resistance is needed to support technology development and to understand its impact on RF performance. This is especially true…”
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    Conference Proceeding
  9. 9

    A hybridised, multi-channel, charged-particle detecting and counting array by Hatfield, J.V., Comer, J., York, T.A., Hicks, P.J.

    “…A hybrid circuit is reported which is a novel position-sensitive charged-particle detector. Multiple-anode integrated detectors (MAIDs) have been developed…”
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    Conference Proceeding
  10. 10

    Random address 3232 programmable analog vector-matrix multiplier for artificial neural networks by Moon, K.K., Kub, F.J., Mack, I.A.

    “…A randomly addressable and programmable 32*32 analog vector-matrix multiplier was designed and fabricated using a standard 2 mu m p-well CMOS technology. Fully…”
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    Conference Proceeding
  11. 11

    ROOMMS-a relaxation-based, object-oriented, mixed-mode simulator by Watts, J.A., Kwasniewski, T.A.

    “…A novel simulator has been developed to facilitate vertical circuit design integration. Written in Objective C, it allows the incorporation of new…”
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    Conference Proceeding
  12. 12

    A universal test sequence for CMOS scan registers by Lee, K.-J., Breuer, M.A.

    “…A systematic method for analyzing all possible faults within the scan path of a scan-based CMOS circuit is given. The analysis shows that both logic and…”
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    Conference Proceeding
  13. 13

    Crosstalk analysis of high-speed interconnects and packages by You, H., Soma, M.

    “…An approach to the crosstalk analysis of high-speed interconnects has been developed. The method yields closed-form expressions of the voltage and current…”
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    Conference Proceeding
  14. 14

    Design of VLSI switch for highly parallel multiprocessor system by Hsu, Y., Benveniste, C., Ruedinger, J., Tan, C.J.

    “…The design of a large, multistage interconnection network that has been successfully constructed and used in a version of the RP3 system is described. The…”
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  15. 15

    An 8-b 50-MHz 225-mW submicron CMOS ADC using saturation eliminated comparators by Matsuura, T., Kojima, H., Imaizumi, E., Usui, K., Ueda, S.

    “…The fastest, low-power 8-b CMOS subranging A/D converter with a 50-MHz conversion rate and 225-mW power consumption is realized using 0.8- mu m CMOS…”
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  16. 16

    PEST-a tool for implementing pseudo-exhaustive self test by Wu, E.

    “…Pseudo-exhaustive self-test (PEST) is a built-in self-test (BIST) methodology. This methodology guarantees 100% stuck-at fault coverage without fault…”
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    Conference Proceeding
  17. 17

    A preprogrammed artificial neural network architecture in signal processing by Bloomer, J., Frank, P.A., Engeler, W.

    “…A mask-programmable artificial neural network (ANN) chip architecture, the tile-based ANN chip assembly, test and simulation results, and use it in signal…”
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  18. 18

    Implementation of a neuron dedicated to Kohonen maps with learning capabilities by Hochet, B., Peiris, V., Corbaz, G., Declercq, M.

    “…A compact implementation of Kohonen-oriented neurons with learning capability, using both analog and digital techniques, with standard low-cost CMOS…”
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    Conference Proceeding
  19. 19

    Novel fault-tolerant circuits for configurable mass memories by Haraszti, T.P., Mento, R.P., Grant, W.N.

    “…Innovative orthogonal shuffle circuits, error correction by weighted codes, associative iterative repair, configurable modular architecture, and hierarchical…”
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  20. 20

    A 40 MHz programmable and reconfigurable filter processor by Cai, M.M., Luthi, D.A., Ruetz, P.A., Ang, P.H.

    “…A programmable and reconfigurable filter processor comprising four 16*16 multiplier-accumulators is presented. The processor, fabricated in a 1.5- mu m 2-layer…”
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    Conference Proceeding