Search Results - "IEEE International SOC Conference, 2004. Proceedings"
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1
Analysis and design of monolithic, high PSR, linear regulators for SoC applications
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…Linear regulators are critical analog blocks that shield a system from fluctuations in supply rails and the importance of determining their power supply…”
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2
An asynchronous on-chip network router with quality-of-service (QoS) support
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…This paper presents an asynchronous on-chip network router with quality-of-service (QoS) support. The router uses a virtual channel architecture with a…”
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3
A power-aware scalable pipelined Booth multiplier
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…Energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless…”
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4
A virtual channel router for on-chip networks
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…This paper proposes an architecture of a virtual channel router for an on-chip network. The router has simple dynamic arbitration which is deterministic and…”
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5
An optically differential reconfigurable gate array using a 0.18 /spl mu/m CMOS process
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…This paper presents the design of a high-density optically differential reconfigurable gate array (ODRGA) using a 0.18/spl mu/m-5 metal CMOS process…”
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6
Bandgap yield loss due to dislocations on RFSiGe transceiver ICs: failure analysis, design
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…New design and layout methods were developed to overcome yield loss from dislocation defects, which are omnipresent in SiGe technologies as a penalty for the…”
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7
A 0.13/spl mu/m 1Gb/s/channel store-and-forward network on-chip
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…A parametric packed-switched scalable network on chip allows energy/throughput/latency tradeoff for data-intensive communication-centric systems. At a clock…”
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8
An embedded read only memory architecture with a complementary and two interchangeable power/performance design points
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…This paper focuses on the features of a 0.13 /spl mu/m embedded, compilable read only memory (ROM). A complementary array cell is described which increases and…”
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Video transmission through domain specific reconfigurable architecurtes over short distance wireless medium utilizing Bluetooth IEEE 802.15.1/spl trade/ standard [architecurtes read architectures]
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…This paper describes efficient video transmission over Bluetooth using reconfigurable architectures. Currently most of the hardware solutions in research…”
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10
VLSI design and analysis of a critical-band processor for speech recognition
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…The critical-band analysis plays a very important role in the frond-end feature extraction for speech recognition. In this paper, a generic low-power and…”
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11
A memory allocation and assignment method using multiway partitioning
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…In many data-intensive applications, an area and power efficient memory architecture is significant for the overall system in terms of area and power…”
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12
A generic reconfigurable neural network architecture as a network on chip
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…Neural networks are widely used in pattern recognition, security applications and data manipulation. We propose a hardware architecture for a generic neural…”
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13
A 3.8Ghz channel-select filter using 0.18/spl mu/m CMOS
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…A high gain bandpass filter was designed as a channel-select filter for applications around 3.8GHz. Three stages of 2nd order were cascaded to have a high…”
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14
Battery-efficient task execution on portable reconfigurable computing
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…We present a battery-efficient task execution methodology for portable reconfigurable computing (RC) platforms. We implement a given algorithm with varying…”
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15
Design of a programmable cryptoprocessor for multiple cryptosystems
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…We propose a programmable architecture for cryptography coprocessors with a 32 bit I/O interface. The coprocessor consists of a programmable finite field…”
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16
Communication on a segmented bus
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…In this study, we discuss communication aspects concerning a segmented bus platform. Placed somewhere midway between the classical system bus and the network…”
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17
Fast techniques for standby leakage reduction in MTCMOS circuits
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…Technology scaling causes subthreshold leakage currents to increase exponentially. Therefore, effective leakage minimization techniques must be designed. In…”
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18
Rapid energy estimation of computations on FPGA based soft processors
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…FPGA based soft processors are an attractive option for implementing embedded applications. As energy efficiency has become a key performance metric,…”
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19
On-chip network based embedded core testing
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…In this paper, network-based embedded core testing (NET) architecture is proposed. The test of individual embedded cores and their interconnection are possible…”
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20
A high-speed power and resolution adaptive flash analog-to-digital converter
Published in IEEE International SOC Conference, 2004. Proceedings (2004)“…A high-speed and small-area power and resolution adaptive flash ADC is presented. The high-speed power and resolution adaptive ADC (HSPRA-ADC) utilizes an…”
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