Search Results - "IEEE International Electron Devices Meeting 2003"

Assessment of Ge n-MOSFETs by quantum simulation by Rahman, A., Ghosh, A., Lundstrom, M.

“…Quantum simulations of ultra-thin-body (UTB), double-gate (DG), end of the ITRS-2001 roadmap germanium n-MOSFETs are performed using the non-equilibrium…”
Get full text

Implementation of temperature dependent contact resistance model for the analysis of deep submicron devices under ESD by Jung-Hoon Chun, Yang Liu, Duvvury, C., Dutton, R.W.

“…The specific contact resistance (/spl rho//sub c/) at the metal/semiconductor interface is known to be a monotonically decreasing function of temperature…”
Get full text

Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects [MOSFETs] by Hane, M., Ikezawa, T., Ezaki, T.

“…Using newly developed simulation tools for the precise design of sub-100 nm MOSFETs, intrinsic statistical fluctuations in device characteristics were…”
Get full text

Closed-loop cooling technologies for microprocessors by Upadhya, G., Zhou, P., Goodson, K., Munch, M., Kenny, T.

“…Recent trends for next generation microprocessors clearly point to significant increase in power consumption, heat density, and to corresponding challenges in…”
Get full text

Predictive spiral inductor compact model for frequency and time domain by Tiemeijer, L.F., Havens, R.J., de Kort, R., Bouttement, Y., Deixler, P., Ryczek, M.

“…A highly accurate predictive inductor model for integrated symmetric inductors with center tap and patterned ground shield is presented. This model is based on…”
Get full text

Optimized strained Si/strained Ge dual-channel heterostructures for high mobility P- and N-MOSFETs by Lee, M.L., Fitzgerald, E.A.

“…Strained Si/strained Ge double heterostructures grown on relaxed Si/sub 1-x/Ge/sub x/ can be used to fabricate extremely high mobility P-MOSFETs. We present…”
Get full text

SETMOS: a novel true hybrid SET-CMOS high current Coulomb blockade oscillation cell for future nano-scale analog ICs by Mahapatra, S., Pott, V., Ecoffey, S., Schmid, A., Wasshuber, C., Tringe, J.W., Leblebici, Y., Declercq, M., Banerjee, K., Ionescu, A.M.

“…We have proposed and validated a true hybrid SET/CMOS device, called SETMOS, that is able to extend the Coulomb blockade oscillations of a SET transistor into…”
Get full text

A simple and high-performance 130 nm SOI eDRAM technology using floating-body pass-gate transistor in trench-capacitor cell for system-on-a-chip (SoC) applications by Kumar, M., Steigerwalt, M.D., Walsh, B.L., Doney, T.L., Wildrick, D., Bard, K.A., Dobuzinsky, D.M., McFarland, P.A., Schiller, C.E., Messenger, B., Rathmill, S.E., Gasasira, A.R., Parries, P.C., Iyer, S.S., Chaloux, S.E., Ho, H.L.

“…This paper, for the first time, reports a fully-functional 130 nm trench-based eDRAM (embedded DRAM), built in unpatterned SOI. The functionality of the eDRAM…”
Get full text

Advancements in complementary carbon nanotube field-effect transistors by Javey, A., Qian Wang, Woong Kim, Hongjie Dai

“…High performance p- and n-type single-walled carbon nanotube (SWNT) field-effect transistors (FETs) are obtained by using high and low work function metals, Pd…”
Get full text

UHF micromechanical extensional wine-glass mode ring resonators by Yuan Xie, Sheng-Shian Li, Yu-Wei Lin, Zeying Ren, Nguyen, C.T.C.

“…Vibrating polysilicon micromechanical ring resonators, utilizing a unique extensional wine-glass mode shape to achieve lower impedance than previous UHF…”
Get full text

Performance comparison of sub 1 nm sputtered TiN/HfO/sub 2/ nMOS and pMOSFETs by Tsai, W., Ragnarsson, L.-A., Pantisano, L., Chen, P.J., Onsia, B., Schram, T., Cartier, E., Kerber, A., Young, E., Caymax, M., De Gendt, S., Heyns, M.

“…HfO/sub 2/ nMOSFETs and pMOSFETs were fabricated using scaled chemical oxides as a starting interface, together with sputtered (PVD) TiN gate electrodes…”
Get full text

Current status of the phase change memory and its future by Lai, S.

“…With the increasing challenge of scaling floating gate nonvolatile memory technology to beyond 65 nm, alternative memory technologies are being investigated…”
Get full text

Organic materials for high-density non-volatile memory applications by Sezi, R., Walter, A., Engl, R., Maltenberger, A., Schumann, J., Kund, M., Dehm, C.

“…This paper describes organic charge transfer complexes exhibiting conductance switching and their potential for use as an active layer in high density…”
Get full text

Few electron memories: finding the compromise between performance, variability and manufacturability at the nano-scale by Silva, H., Kim, M.K., Kumar, A., Avci, U., Tiwari, S.

“…The key challenges for memories that operate at the nanoscale, and are compatible with mainstream nano-scale CMOS, are in achieving the performance…”
Get full text

Nano transformations: a future of our making by Bordogna, J.

“…"Nano" denotes the very small in scale, but there is nothing diminutive about the expectations generated by nanotech-the application of fundamental research at…”
Get full text

Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform by Tavel, B., Bidaud, M., Emonet, N., Barge, D., Planes, N., Brut, H., Roy, D., Vildeuil, J.C., Difrenza, R., Rochereau, K., Denais, M., Huard, V., Llinares, P., Bruyere, S., Parthasarthy, C., Revil, N., Pantel, R., Guyader, F., Vishnubotla, L., Barla, K., Arnaud, F., Stolk, P., Woo, M.

“…This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data…”
Get full text

70nm NAND flash technology with 0.025 /spl mu/m/sup 2/ cell size for 4Gb flash memory by Yong-Sik Yim, Kwang-Shik Shin, Sung-Hoi Hur, Jae-Duk Lee, Ihn-Gee Balk, Hong-Soo Kim, Soo-Jin Chai, Eun-Young Choi, Min-Cheol Park, Dong-Seok Eun, Sung-Bok Lee, Hye-Jin Lim, Sun-Pil Youn, Sung-Hun Lee, Tae-Jung Kim, Han-Soo Kim, Kyu-Charn Park, Ki-Nam Kim

“…A 4 Gb NAND flash memory with a 70 nm design rule is developed for mass storage applications. The cell size is 0.025 /spl mu/m/sup 2/, which is the smallest…”
Get full text

Thousands of microcantilevers for highly parallel and ultra-dense data storage by Vettiger, P., Albrecht, T., Despont, M., Drechsler, U., Durig, U., Gotsmann, B., Jubin, D., Haberle, W., Lantz, M.A., Rothuizen, H., Stutz, R., Wiesmann, D., Binnig, G.K., Bachtold, P., Cherubini, G., Hagleitner, C., Loeliger, T., Pantazi, A., Pozidis, H., Eleftheriou, E.

“…Ultrahigh storage densities of up to 1 Tb/in./sup 2/ or more can be achieved by using local-probe techniques to write, read back, and erase data in very thin…”
Get full text

ALD HfO/sub 2/ using heavy water (D/sub 2/O) for improved MOSFET stability by Tseng, H.-H., Ramon, M.E., Hebert, L., Tobin, P.J., Triyoso, D., Grant, J.M., Jiang, Z.X., Roan, D., Samavedam, S.B., Gilmer, D.C., Kalpat, S., Hobbs, C., Taylor, W.J., Adetutu, O., White, B.E.

“…Device instability is one of the most challenging issues to implement high-k gate dielectrics. Incorporation of deuterium during the ALD (atomic layer…”
Get full text

Organic semiconductor RFID transponders by Baude, P.F., Ender, D.A., Kelley, T.W., Haase, M.A., Muyres, D.V., Theiss, S.D.

“…We present pentacene-based radio frequency identification (RFID) transponder circuitry, patterned entirely using flexible shadow-masks, and operating at RF…”
Get full text