Search Results - "Hwang, Kihyun"

Electrical characteristics of SiO2/ZrO2 hybrid tunnel barrier for charge trap flash memory by Choi, Jaeho, Bae, Juhyun, Ahn, Jaeyoung, Hwang, Kihyun, Chung, Ilsub

“…In this paper, we investigate the electrical characteristics of SiO2/ZrO2 hybrid tunnel oxide in metal-Al2O3-SiO2-Si3N4-SiO2-silicon (MAONOS) structure in an…”
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Ge surface-energy-driven secondary grain growth via two-step annealing by Lee, Sangsoo, Son, Yong-Hoon, Park, Yongjo, Hwang, Kihyun, Shin, Yoo Gyun, Yoon, Euijoon

“…A two-step annealing method with a low thermal budget is proposed for advanced surface-energy-driven secondary grain growth of Ge films without any…”
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Hole trap effect on time-dependent-dielectric breakdown (TDDB) of high-voltage peripheral nMOSFETs in flash memory application by Guangfan Jiao, Sungkweon Baek, Kab-jin Nam, Sung-Il Chang, Siyeon Cho, Kauerauf, Thomas, Chanho Lee, Seung-Uk Han, Jin-Soak Kim, Eun-Ae Chung, Yoo-Cheol Shin, Junhee Lim, Yu-Gyun Shin, Kihyun Hwang

“…In this work, the TDDB mechanism in high-voltage nMOSFETs with high-density of pre-existing defects in the gate oxide is investigated. In contrast to the…”
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Advanced Si solid phase crystallization for vertical channel in vertical NANDs by Lee, Sangsoo, Son, Yong-Hoon, Hwang, Kihyun, Shin, Yoo Gyun, Yoon, Euijoon

“…The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in…”
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Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash by Bio Kim, Seung-Hyun Lim, Dong Woo Kim, Nakanishi, T, Sangryol Yang, Jae-Young Ahn, HanMei Choi, Kihyun Hwang, Yongsun Ko, Chang-Jin Kang

“…We have investigated thin film transistors (TFTs) with ultra-thin polycrystalline silicon (poly-Si) of 77 Å - 185 Å. The TFT charge transfer characteristics…”
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Cu Microstructure of High Density Cu Hybrid Bonding Interconnection by Kim, Seokho, Kang, Pilkyu, Kim, Taeyeong, Lee, Kyuha, Jang, Joohee, Moon, Kwangjin, Na, Hoonjoo, Hyun, Sangjin, Hwang, Kihyun

“…The scaling of semiconductor device below 10nm has faced the higher process difficulty and longer development periods. Three-dimensional integrated circuits…”
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Origins of wear-induced tungsten corrosion defects in semiconductor manufacturing during tungsten chemical mechanical polishing by Choi, Seung-Hoon, Kreider, Melissa E., Nielander, Adam C., Stevens, Michaela Burke, Kamat, Gaurav, Koo, Ja Eung, Bae, Ki Ho, Kim, Hoyoung, Yoon, Il Young, Yoon, Bo Un, Hwang, Kihyun, Lee, Dong Un, Jaramillo, Thomas F.

“…[Display omitted] •W contact plugs in CMOS IC wafers have been found to undergo corrosion.•Mismatch in the CMP processing times results in extended DI rinsing…”
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Effect of Millisecond Annealing Temperature of Ni1-xPtx Si Formation on Leakage Current Characteristics of Static Random- Access Memory Cells by Kim, Jinbum, Park, Taejin, Lee, Seounghoon, Lee, Siyoung, Kim, Chulsung, Hyun, Sangjin, Kim, Yihwan, Hwang, Kihyun, Kim, Hyoungsub

“…The importance of optimizing the millisecond annealing (MSA) temperature for Pt-doped NiSi (<inline-formula> <tex-math notation="LaTeX">{\mathrm…”
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Effect of Millisecond Annealing Temperature of Ni1- x Pt x Si Formation on Leakage Current Characteristics of Static Random- Access Memory Cells by Kim, Jinbum, Park, Taejin, Lee, Seounghoon, Lee, Siyoung, Kim, Chulsung, Hyun, Sangjin, Kim, Yihwan, Hwang, Kihyun, Kim, Hyoungsub

“…The importance of optimizing the millisecond annealing (MSA) temperature for Pt-doped NiSi ([Formula Omitted]Pt x Si) contact formation was highlighted by…”
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Effect of Millisecond Annealing Temperature of Ni 1- x Pt x Si Formation on Leakage Current Characteristics of Static Random- Access Memory Cells by Kim, Jinbum, Park, Taejin, Lee, Seounghoon, Lee, Siyoung, Kim, Chulsung, Hyun, Sangjin, Kim, Yihwan, Hwang, Kihyun, Kim, Hyoungsub

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Electrical characteristics of SiO 2 /ZrO 2 hybrid tunnel barrier for charge trap flash memory by Choi, Jaeho, Bae, Juhyun, Ahn, Jaeyoung, Hwang, Kihyun, Chung, Ilsub

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Electrical characteristics of SiO^sub 2^/ZrO^sub 2^ hybrid tunnel barrier for charge trap flash memory by Choi, Jaeho, Bae, Juhyun, Ahn, Jaeyoung, Hwang, Kihyun, Chung, Ilsub

“…In this paper, we investigate the electrical characteristics of SiO2/ZrO2 hybrid tunnel oxide in metal–Al2O3–SiO2–Si3N4–SiO2–silicon (MAONOS) structure in an…”
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Pt-doped Ni-silicide films formed by pulsed-laser annealing: Microstructural evolution and thermally robust Ni1-xPtxSi2 formation by Kim, Jinbum, Shin, Ilgyou, Park, Taejin, Kim, Jinyong, Choi, Seongheum, Lee, Sungho, Hong, Seongpyo, Lee, Hyung-Ik, Won, Jung Yeon, Kim, Taegon, Kim, Yihwan, Hwang, Kihyun, Lee, Hoo-Jeong, Kim, Hyoungsub

“…Pulsed-laser annealing (PLA) was performed on a preformed Pt-doped Ni-rich silicide film (Ni2Si phase), and its microstructural and phase evolution were…”
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Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB by Guangfan Jiao, Toledano-Luque, Maria, Kab-Jin Nam, Toshiro, Nakanishi, Seung-Hun Lee, Jin-Soak Kim, Kauerauf, Thomas, EunAe Chung, Dong-il Bae, Geumjong Bae, Dong-Won Kim, Kihyun Hwang

“…In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative…”
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Embedded STT-MRAM in 28-nm FDSOI Logic Process for Industrial MCU/IoT Application by Lee, Yong Kyu, Jung, Hyunsung, Lee, Kilho, Shin, HyunChul, Jung, Hyuntaek, Pyo, Mark, Antonyan, Artur, Lee, Daesop, Hwang, Sohee, Jang, Daehyun, Ji, Yongsung, Song, Yoonjong, Lee, Seungbae, Lim, Jungman, Koh, Kwan-Hyeob, Hwang, Kihyun, Hong, Hyeongsun, Park, Kichul, Jeong, Gitae, Yoon, Jong Shik, Jung, E.S., Kim, JooChan, Oh, SeChung, Bae, Byoung-Jae, Lee, SangHumn, Lee, JungHyuk, Pi, UngHwan, Seo, Boyoung

“…We demonstrate, for the first time, 28-nm embedded STT-MRAM operating at full industrial temperature range (-40~125°C) with >1E+6 endurance and >10 year…”
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Lamellar-structured Ni-silicide film formed by eutectic solidification by Kim, Jinbum, Jung, Younheum, Lee, Sungho, Hong, Seongpyo, Choi, Seongheum, Kim, Jinyong, Park, Taejin, Lee, Eunha, Won, Jung Yeon, Lee, Hyung-Ik, Lee, Yun Jae, Kim, Bosung, Kim, Joong Jung, Kim, Yihwan, Hwang, Kihyun, Yang, Cheol-Woong, Kim, Hyoungsub

“…Pt-doped NiSi‒NiSi2 thin films in a uniform lamellar structure with a periodicity on the scale of a few tens of nanometers were formed on Si(001) substrates…”
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Observation of heterostructure epitaxy of Pt-doped Ni-monosilicide on Si(001) by Kim, Jinbum, Lee, Hyangsook, Kim, Jung-Hwa, Shin, Ilgyou, Yoo, Jeongho, Kim, Seokhoon, Choi, Seongheum, Kim, Jinyong, Park, Taejin, Kim, Yihwan, Hwang, Kihyun, Lee, Eunha, Kim, Hyoungsub

“…The objective of this study was to determine detailed microstructure of a Ni1–xPtxSi film formed via a melting/quenching process using high temperature laser…”
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Analysis of trap distribution in polysilicon channel transistors using the variable amplitude charge pumping method by Nguyen, Manh-Cuong, Jeon, Yoon-Seok, Tong, Duc-Tai, You, Seung-Won, Jeong, Jae-Kyeong, Kim, Bio, Ahn, Jae-young, Hwang, Kihyun, Choi, Rino

“…•Proposing a novel method to determine the trap distribution in poly-Si channel MOSFETs.•Demonstrating the validity of the method using MOSFETs with various…”
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A 1280×960 Dynamic Vision Sensor with a 4.95-μm Pixel Pitch and Motion Artifact Minimization by Suh, Yunjae, Choi, Seungnam, Ito, Masamichi, Kim, Jeongseok, Lee, Youngho, Seo, Jongseok, Jung, Heejae, Yeo, Dong-Hee, Namgung, Seol, Bong, Jongwoo, Yoo, Sehoon, Shin, Seung-Hun, Kwon, Doowon, Kang, Pilkyu, Kim, Seokho, Na, Hoonjoo, Hwang, Kihyun, Shin, Changwoo, Kim, Jun-Seok, Park, Paul K. J., Kim, Joonseok, Ryu, Hyunsurk, Park, Yongin

“…This paper reports a 1280×960 DVS. A 4.95-μm pixel pitch is achieved with in-pixel Cu-Cu connection and the newly designed GIDL-suppression scheme. A…”
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Highly-reliable NAND flash memory using Al2O3-inserted inter-poly dielectric by Sung-Hae Lee, Bonyoung Koo, Kihyun Hwang, Siyoung Choi, Joo-tae Moon

“…The improvement of device performances has been achieved successfully through OAO IPD EOT scaling, which shows that OAO IPD is applicable to sub-40nm devices…”
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