Search Results - "Huynh, Sharon"
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Relative Validity of the Eat and Track (EaT) Smartphone App for Collection of Dietary Intake Data in 18-to-30-Year Olds
Published in Nutrients (14-03-2019)“…(1) Background: Smartphone dietary assessment apps can be acceptable and valid data collection methods but have predominantly been validated in highly educated…”
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Journal Article -
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Treatment during a developmental window prevents NF1-associated optic pathway gliomas by targeting Erk-dependent migrating glial progenitors
Published in Developmental cell (25-10-2021)“…The mechanism of vulnerability to pediatric low-grade gliomas (pLGGs)—the most common brain tumor in children—during development remains largely unknown. Using…”
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Journal Article -
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A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology
Published in IEEE journal of solid-state circuits (01-01-2009)“…A 16 Gb 4-state MLC NAND flash memory augments the sustained program throughput to 34 MB/s by fully exercising all the available cells along a selected word…”
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Journal Article Conference Proceeding -
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A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate
Published in IEEE journal of solid-state circuits (01-01-2009)“…A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3)…”
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Journal Article Conference Proceeding -
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128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode
Published in 2012 IEEE International Solid-State Circuits Conference (01-02-2012)“…This paper addresses challenges with improvements made over previous NAND generations to achieve high performance while maintaining a low fail-bit count (FBC)…”
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Conference Proceeding -
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A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01-02-2008)“…We present an 8 MB/s 3-bit per cell (D3) NAND flash memory that uses the same number of ECC bytes as 2-bit per cell (D2) NAND. Since no extra columns are added…”
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Conference Proceeding -
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A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01-02-2008)“…In the diverse world of NAND flash applications, higher storage capacity is not the only imperative. Increasingly, performance is a differentiating factor and…”
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Conference Proceeding