Search Results - "Hurst, P.J."
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1
Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs
Published in IEEE transactions on circuits and systems. I, Regular papers (01-09-2009)“…Bandwidth mismatch between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) causes undesirable distortions in the…”
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2
Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter
Published in IEEE transactions on circuits and systems. I, Regular papers (01-01-2004)“…Offset mismatch, gain mismatch, and sample-time error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters…”
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3
Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver
Published in IEEE transactions on circuits and systems. I, Regular papers (01-02-2009)“…In this paper, techniques to overcome the errors caused by the offset, gain, sample-time, and bandwidth mismatches among time-interleaved analog-to-digital…”
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4
Reconstruction of band-limited periodic nonuniformly sampled signals through multirate filter banks
Published in IEEE transactions on circuits and systems. I, Regular papers (01-08-2004)“…A band-limited signal can be recovered from its periodic nonuniformly spaced samples provided the average sampling rate is at least the Nyquist rate. A…”
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5
A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration
Published in IEEE journal of solid-state circuits (01-12-2002)“…Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a…”
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6
A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration
Published in IEEE journal of solid-state circuits (01-05-2005)“…This paper presents a prototype analog-to-digital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closed-loop gain errors,…”
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7
A Level-Crossing Analog-to-Digital Converter With Triangular Dither
Published in IEEE transactions on circuits and systems. I, Regular papers (01-09-2009)“…In this paper, a level-crossing analog-to-digital converter is described. It can convert audio bandwidth signals with high resolution using few threshold…”
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8
A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration
Published in IEEE journal of solid-state circuits (01-11-2004)“…A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the…”
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9
A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters
Published in IEEE journal of solid-state circuits (01-01-2009)“…Piezoelectric transducers are a viable way of harvesting vibrational energy for low power embedded systems such as wireless sensors. A proposed disk-shaped…”
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10
Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA
Published in IEEE journal of solid-state circuits (01-10-2009)“…To reduce power dissipation, the input sample-and-hold amplifier (SHA) is eliminated in a pipelined analog-to-digital converter (ADC) with nested background…”
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11
Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters
Published in IEEE transactions on circuits and systems. II, Express briefs (01-10-2006)“…The sample-and-hold amplifier in each channel of a time-interleaved analog-to-digital converter system has finite bandwidth, and these bandwidths may be…”
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12
Digital background calibration for memory effects in pipelined analog-to-digital converters
Published in IEEE transactions on circuits and systems. I, Regular papers (01-03-2006)“…Memory errors can occur in the stages of a pipelined analog-to-digital converter (ADC) due to several effects. These include capacitor dielectric…”
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13
A digital background calibration technique for time-interleaved analog-to-digital converters
Published in IEEE journal of solid-state circuits (01-12-1998)“…A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 /spl mu/m CMOS…”
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14
Digital Calibration of a Nonlinear S/H
Published in IEEE journal of selected topics in signal processing (01-06-2009)“…Sample and hold (S/H) circuits exhibit a nonlinear behavior due to the input signal dependence of the sampling switch. In this paper, we develop a mixed signal…”
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15
DAC Quantization-Noise Cancellation in an Echo-Canceling Transceiver
Published in IEEE transactions on circuits and systems. II, Express briefs (01-02-2008)“…Data converters, in particular, the transmit digital-to-analog converter (DAC), should not limit performance in a full-duplex digital-communication…”
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16
Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver
Published in IEEE transactions on circuits and systems. II, Express briefs (01-10-2009)“…Two approaches to calibrate a pipelined analog-to-digital converter (ADC) and adapt an equalizer in a baseband receiver are proposed. Adaptive digital…”
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17
An analog background calibration technique for time-interleaved analog-to-digital converters
Published in IEEE journal of solid-state circuits (01-12-1998)“…Analog background calibration using adaptive signal processing, an extra channel, and mixed signal integrators matches the offsets and gains of…”
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18
Background interstage gain calibration technique for pipelined ADCs
Published in IEEE transactions on circuits and systems. I, Regular papers (01-01-2005)“…A background self-calibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic…”
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19
Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers
Published in IEEE transactions on circuits and systems. I, Regular papers (01-02-2004)“…Several Miller compensation schemes using a current buffer in series with the compensation capacitor to modify the right-half-plane zero in fully differential…”
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20
A Programmable Impedance Matching Circuit for Voiceband Modems
Published in IEEE journal of solid-state circuits (01-02-2008)“…A line impedance-matching circuit for a voiceband modem is described. The circuit can be programmed to realize four different impedances. A switched-capacitor…”
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