Search Results - "Hur, Sunghoi"
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A Study of High-Voltage p-Type MOSFET Degradation Under AC Stress
Published in IEEE transactions on electron devices (01-09-2015)“…In this paper, the degradation characteristics of high-voltage (HV) p-type MOSFETs are investigated during negative unipolar ac stress on the gate electrode…”
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Journal Article -
2
A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory
Published in 2010 Symposium on VLSI Technology (01-06-2010)“…A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics…”
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Conference Proceeding
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3
Kernel Smoothing Technique Based on Multiple-Coordinate System for Screening Potential Failures in NAND Flash Memory
Published in 2023 IEEE 41st VLSI Test Symposium (VTS) (24-04-2023)“…With the growing complexity of integrated circuits and increasing capacity of memory devices, it is becoming increasingly difficult to screen out all defective…”
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Conference Proceeding -
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Mechanical Stress Effects on Dielectric Leakage and Interconnection Integrity in 3D NAND Flash Memory
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (16-06-2024)“…This paper presents a comprehensive study of stress-induced leakage in dielectrics, combining structural analysis with electrical transport properties in the…”
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Conference Proceeding -
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A new approach for trap analysis of vertical NAND flash cell using RTN characteristics
Published in 2014 IEEE International Electron Devices Meeting (01-12-2014)“…We introduce new phenomena that show turn-on at back-side for Vertical NAND (V-NAND) with back-insulator and propose a new method to analyze the trap of…”
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Conference Proceeding -
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High Bit Cost Scalability and Reliable Cell Characteristics for 7th Generation 1Tb 4Bit/Cell 3D-NAND Flash
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11-06-2023)“…The continuous increase of total number of word-line (WL) layers and the reduction of unit cell size make it difficult to implement quad-level cell (QLC) in…”
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Conference Proceeding -
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A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11-06-2023)“…A 1.2 V, 3.0 Gb/s/pin 16Tb NAND flash memory package with proposed 4 th generation F-chip is presented. It is implemented with self-training techniques such as…”
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Conference Proceeding -
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Physical Modeling and Analysis on Improved Endurance Behavior of P-Type Floating Gate NAND Flash Memory
Published in 2012 4th IEEE International Memory Workshop (01-05-2012)“…In this work, we report improved endurance of p-type floating-gate NAND flash cell. The physical model on the endurance and data retention of p-type…”
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Conference Proceeding -
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A New Cell-to-Cell Interference Induced by Conduction Band Distortion near S/D Region in Scaled NAND Flash Memories
Published in 2011 3rd IEEE International Memory Workshop (IMW) (01-05-2011)“…A new cell-to-cell interference phenomenon has been found beyond sub 40nm node. Unlike capacitive coupling between floating gates, the threshold voltage (V TH…”
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Conference Proceeding -
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Highly Manufacturable 7th Generation 3D NAND Flash Memory with COP structure and Double Stack Process
Published in 2021 Symposium on VLSI Technology (13-06-2021)“…A novel 3D NAND Flash memory device with 17X WL (Word line) layers has been successfully developed. COP(Cell Over Peripheral) Structure has been applied,…”
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Conference Proceeding -
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A Noble Design Methodology to Minimize Plasma Induced Damage Using a Distributed Network Model in VNAND Flash Memory
Published in 2023 International Electron Devices Meeting (IEDM) (09-12-2023)“…As the number of word-line layers increases in 3D NAND to improve bit density, the design of By-pass Via (BVia) becomes more difficult due to the increased…”
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Conference Proceeding -
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Highly Reliable Cell Characteristics with CSOB(Channel-hole Sidewall ONO Butting) Scheme for 7th Generation 3D-NAND
Published in 2021 IEEE International Electron Devices Meeting (IEDM) (11-12-2021)“…Architecture change from BCS (Body Contact Spacer) scheme to CSOB (Channel-hole Sidewall ONO Butting) scheme for the 7th-generation 3D-NAND flash memory is…”
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Conference Proceeding -
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Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND
Published in 2023 IEEE International Memory Workshop (IMW) (01-05-2023)“…We propose a novel structure to enhance transverse band-to-band tunneling (T-BTBT) for the erase scheme assisted by gate induced drain leakage (GIDL) to…”
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Conference Proceeding -
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Process Improvements for 7th Generation 1Tb Quad-Level Cell 3D NAND Flash Memory in Mass Production
Published in 2023 IEEE International Memory Workshop (IMW) (01-05-2023)“…Over the past few decades, a greater need for 3D Vertical NAND (V-NAND) flash memory storage capacity has emerged. Compared to its prevailing technical…”
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Conference Proceeding -
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The new program/erase cycling degradation mechanism of NAND flash memory devices
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01-12-2009)“…NAND memory cells scaled to 51-32 nm, when they receive stress due to program and erase cycles, not only reveal a gradual positive shift of a midgap voltage in…”
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Conference Proceeding