Search Results - "Hur, Ibrahim"

Memory Prefetching Using Adaptive Stream Detection by Hur, Ibrahim, Lin, Calvin

“…We present Adaptive Stream Detection, a simple technique for modulating the aggressiveness of a stream prefetcher to match a workload's observed spatial…”
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Adaptive History-Based Memory Schedulers by Hur, Ibrahim, Lin, Calvin

“…As memory performance becomes increasingly important to overall system performance, the need to carefully schedule memory operations also increases. This paper…”
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Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model by Eyerman, Stijn, Heirman, Wim, Hur, Ibrahim

“…Accurately modeling memory timing in a processor simulator is crucial for obtaining accurate and useful performance predictions. DRAM has a complex timing and…”
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HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures by Gerogiannis, Gerasimos, Aananthakrishnan, Sriram, Torrellas, Josep, Hur, Ibrahim

“…Sparse Matrix Dense Matrix Multiplication (SpMM) is an important kernel with application across a wide range of domains, including machine learning and linear…”
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The Intel® Programmable and Integrated Unified Memory Architecture (PIUMA) Graph Analytics Processor by Aananthakrishnan, Sriram, Abedin, Shamsul, Cave, Vincent, Checconi, Fabio, Du Bois, Kristof, Eyerman, Stijn, Fryman, Joshua B., Heirman, Wim, Howard, Jason, Hur, Ibrahim, Jain, Samkit, Landowski, Marek M., Ma, Kevin, Nelson, Jarrod, Pawlowski, Robert, Petrini, Fabrizio, Szkoda, Sebastian, Tayal, Sanjaya, Tithi, Jesmin Jahan, Vandriessche, Yves

“…High performance large scale graph analytics are essential to timely analyze relationships in big data sets. Conventional processor architectures suffer from…”
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RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors by Heirman, Wim, Eyerman, Stijn, Du Bois, Kristof, Hur, Ibrahim

“…Architectural studies of the cache and memory hierarchy need a fast simulation model for the processor core that accurately conveys the impact of memory…”
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Breaking In-Order Branch Miss Recovery by Eyerman, Stijn, Heirman, Wim, Steen, Sam Van den, Hur, Ibrahim

“…Despite very accurate branch predictors, branch misses remain an important source of performance limiters, especially for irregular applications. To ensure…”
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Multi-Stage CPI Stacks by Eyerman, Stijn, Heirman, Wim, Du Bois, Kristof, Hur, Ibrahim

“…CPI stacks are an intuitive way to visualize processor core performance bottlenecks. However, they often do not provide a full view on all bottlenecks, because…”
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A comprehensive approach to DRAM power management by Hur, I., Lin, C.

“…This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three…”
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Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study by Eyerman, Stijn, Hur, Ibrahim

“…Crucial in the performance of microservice applications is the efficient handling of RPC calls. We found that the asynchronous call implementation in a popular…”
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Undersubscribed threading on clustered cache architectures by Heirman, Wim, Carlson, Trevor E., Van Craeynest, Kenzo, Hur, Ibrahim, Jaleel, Aamer, Eeckhout, Lieven

“…Recent many-core processors such as Intel's Xeon Phi and GPGPUs specialize in running highly scalable parallel applications at high performance while…”
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Power-aware multi-core simulation for early design stage hardware/software co-optimization by Heirman, Wim, Sarkar, Souradip, Carlson, Trevor E., Hur, Ibrahim, Eeckhout, Lieven

“…Stringent performance targets and power constraints push designers towards building specialized workload-optimized systems across a broad spectrum of the…”
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DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks by Eyerman, Stijn, Heirman, Wim, Hur, Ibrahim

“…For memory-bound applications, memory bandwidth utilization and memory access latency determine performance. DRAM specifications mention the maximum peak…”
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Accurate and Scalable Many-Node Simulation by Eyerman, Stijn, Heirman, Wim, Bois, Kristof Du, Hur, Ibrahim

“…Accurate performance estimation of future many-node machines is challenging because it requires detailed simulation models of both node and network. However,…”
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Resource-bounded multicore emulation using Beefarm by Arcas, Oriol, Sonmez, Nehir, Sayilar, Gokhan, Singh, Satnam, Unsal, Osman S., Cristal, Adrian, Hur, Ibrahim, Valero, Mateo

“…In this article, we present the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years both in FPGA and…”
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Hash Table Scalability on Intel PIUMA by Seshasayee, Balasubramanian, Fryman, Joshua, Hur, Ibrahim

“…The Intel PIUMA (Programmable and Integrated Unified Memory Architecture) is a scalable, massively multithreaded architecture designed to operate on…”
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Profiling and Optimizing Transactional Memory Applications by Zyulkyarov, Ferad, Stipic, Srdjan, Harris, Tim, Unsal, Osman S., Cristal, Adrián, Hur, Ibrahim, Valero, Mateo

“…Many researchers have developed applications using transactional memory (TM) with the purpose of benchmarking different implementations, and studying whether…”
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Discovering and understanding performance bottlenecks in transactional applications by Zyulkyarov, Ferad, Stipic, Srdjan, Harris, Tim, Unsal, Osman S., Cristal, Adrian, Hur, Ibrahim, Valero, Mateo

“…Many researchers have developed applications using transactional memory (TM) with the purpose of benchmarking different implementations, and studying whether…”
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Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation by Eyerman, Stijn, Steen, Sam Van Den, Heirman, Wim, Hur, Ibrahim

“…Wrong-path speculative execution on an out-oforder processor core has no impact on an application's functionality and correctness, but it can impact…”
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Feedback mechanisms for improving probabilistic memory prefetching by Hur, I., Lin, C.

“…This paper presents three techniques for improving the effectiveness of the recently proposed adaptive stream detection (ASD) prefetching mechanism. The ASD…”
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