Search Results - "Hung-Chi Fang"
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1
Precompression Quality-Control Algorithm for JPEG 2000
Published in IEEE transactions on image processing (01-11-2006)“…In this paper, a precompression quality-control algorithm is proposed. It can greatly reduce computational power of the embedded block coding (EBC) and memory…”
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Journal Article -
2
Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling
Published in IEEE transactions on signal processing (01-12-2006)“…Memory issues pose the most critical problem in designing a high-performance JPEG 2000 architecture. The tile memory occupies more than 50% area in…”
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Journal Article -
3
High-performance JPEG 2000 encoder with rate-distortion optimization
Published in IEEE transactions on multimedia (01-08-2006)“…An 81 MSamples/s JPEG 2000 single-chip encoder is implemented on 5.5 mm 2 area using 0.25-mum CMOS technology. This IC can losslessly encode HDTV 720p…”
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Journal Article -
4
Word-Level Parallel Architecture of JPEG 2000 Embedded Block Coding Decoder
Published in IEEE transactions on multimedia (01-10-2007)“…This paper presents a word-level decoding architecture of embedded block coding in JPEG 2000. This architecture decodes one coefficient per cycle based on the…”
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Journal Article -
5
Parallel embedded block coding architecture for JPEG 2000
Published in IEEE transactions on circuits and systems for video technology (01-09-2005)“…This paper presents a parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000. The architecture is based on the proposed word-level EBC…”
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Journal Article -
6
Advances in Hardware Architectures for Image and Video Coding - A Survey
Published in Proceedings of the IEEE (01-01-2005)“…This paper provides a survey of state-of-the-art hardware architectures for image and video coding. Fundamental design issues are discussed with particular…”
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Journal Article -
7
Low-delay and error-robust wireless video transmission for video communications
Published in IEEE transactions on circuits and systems for video technology (01-12-2002)“…Video communications over wireless networks often suffer from various errors. A novel video transmission architecture is proposed to meet the low-delay and…”
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Journal Article -
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124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory
Published in IEEE transactions on circuits and systems for video technology (01-04-2007)“…A 124 MSamples/s JPEG 2000 codec is implemented on a 20.1 mm 2 die with 0.18 mum CMOS technology dissipating 385 mW at 1.8 V and 42 MHz. This chip is capable…”
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Journal Article -
9
Algorithm analysis and architecture design for HDTV applications - a look at the H.264/AVC video compressor system
Published in IEEE circuits and devices magazine (01-05-2006)“…In this article, we suggest some techniques to design the H.264/AVC video coding system for HDTV applications. The design exploration is made according to…”
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Journal Article -
10
JPEG, MPEG-4, and H.264 Codec IP Development
Published in Design, Automation and Test in Europe (07-03-2005)“…This paper summarizes our design experiences of various image and video codec IPs. The design issues and methodology of custom video codecs are discussed. The…”
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Conference Proceeding
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A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)“…An H.264/AVC encoder is implemented on a 31.72mm/sup 2/ die with 0.18/spl mu/m CMOS technology. A four-stage macroblock pipelined architecture encodes 720p…”
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Conference Proceeding -
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Architecture of MPEG-7 color structure description generator for realtime video applications
Published in 2004 International Conference on Image Processing, 2004. ICIP '04 (2004)“…Color structure descriptor (CSD) provides satisfactory image indexing and retrieval results among all color-based descriptors in MPEG-7. The superiority comes…”
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Conference Proceeding -
13
High performance two-symbol arithmetic encoder in JPEG 2000
Published in IEEE International Symposium on Consumer Electronics, 2004 (2004)Get full text
Conference Proceeding -
14
Area Efficient Architecture for the Embedded Block Coding in JPEG 2000
Published in 2005 IEEE Asian Solid-State Circuits Conference (01-11-2005)“…An area efficient architecture for the embedded block coding in JPEG 2000 is implemented on a 1.23 mm 2 die using 0.18 mum CMOS technology. This chip can…”
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Conference Proceeding -
15
Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture
Published in 2006 IEEE Workshop on Signal Processing Systems Design and Implementation (01-10-2006)“…In this paper, an area-efficient JPEG 2000 codec is implemented on 6.1 mm 2 with 0.18 mum CMOS technology dissipating 180 mW at 1.8 V and 60 MHz. It is capable…”
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Conference Proceeding -
16
Algorithm analysis and architecture design for HDTV applications
Published in IEEE circuits and devices magazine (01-05-2006)Get full text
Journal Article -
17
Analysis and architecture for memory efficient JBIG2 arithmetic encoder
Published in 48th Midwest Symposium on Circuits and Systems, 2005 (2005)“…JBIG2 is the latest international standard for bilevel image compression. It partitions a bilevel image into three types of region - text, halftone, and…”
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Conference Proceeding -
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81MS/s JPEG2000 single-chip encoder with rate-distortion optimization
Published in 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) (2004)“…An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30…”
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Conference Proceeding -
19
The Seismic Behavior of Steel Structures with Semi-Rigid Diaphragms
Published 01-01-2015“…This thesis investigates the torsional performance of steel structures with and without rigid diaphragm constraints through numerical simulations and evaluates…”
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Dissertation -
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Area efficient architecture for the embedded block coding in JPEG 2000
Published in The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04 (2004)“…An area efficient architecture for the embedded block coding is presented in this paper. A new algorithm is proposed to compute the state variables on-the-fly…”
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Conference Proceeding