Search Results - "Hsieh, Kenny"

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS by Frans, Yohan, Carey, Declan, Erett, Marc, Amir-Aslanzadeh, Hesam, Fang, Wayne Y., Turker, Didem, Jose, Anup P., Bekele, Adebabay, Im, Jay, Upadhyaya, Parag, Wu, Zhaoyin Daniel, Hsieh, Kenny C. H., Savoj, Jafar, Chang, Ken

“…This paper describes a 0.5-16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and…”
Get full text

A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET by Tsai, Tsung-Hsien, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny Cheng-Hsiang, Staszewski, Robert Bogdan

“…All-digital PLLs (ADPLLs) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization noise due to discrete tuning of their…”
Get full text

A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs by Savoj, Jafar, Hsieh, Kenny Cheng-Hsiang, Fu-Tai An, Gong, Jason, Jay Im, Xuewen Jiang, Jose, Anup P., Kireev, Vassili, Siok-Wei Lim, Roldan, Arianne, Turker, Didem Z., Upadhyaya, Parag, Wu, Daniel, Ken Chang

“…This paper describes the design of a 0.5-6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques…”
Get full text

3.8 A 0.65V 900µm² BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from −25°C to 125°C by Lien, Bei-Shing, Liu, Szu Lin, Lai, Wei-Lin, Lu, Yi-Chen, Peng, Yung-Chow, Hsieh, Kenny Cheng-Hsiang

“…To maintain high-performance computing capacity and prevent chip overheating, it is essential to minimize the gap between on-die thermal measurements and the…”
Get full text

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing by Lin, Mu-Shan, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank

“…We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two…”
Get full text

Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS by Chou, Mao-Hsuan, Chang, Ya-Tin, Tsai, Tsung-Hsien, Lu, Tsung-Che, Liao, Chia-Chun, Kuo, Hung-Yi, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny C. H., Loke, Alvin L. S., Chen, Mark

“…We propose an embedded PLL phase noise measurement macro for cost-effective SoC test based on a phase-frequency detector/charge pump (PFD/CP) MASH 1-1-1 ΔΣ…”
Get full text

A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET by Chen, Wei-Chih, Yang, Shu-Chun, Shih, Yu-Nan, Huang, Wen-Hung, Tsai, Chien-Chun, Hsieh, Kenny Cheng-Hsiang

“…A 56Gb/s PAM-4 wireline receiver testchip is demonstrated in 7nm FinFET. The equalization is achieved with four stages continuous time linear equalizer (CTLE)…”
Get full text

A 7-nm 4-GHz Arm^1-Core-Based CoWoS^1 Chiplet Design for High-Performance Computing by Lin, Mu-Shan, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi

“…We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two…”
Get full text

An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology by Lu, Tsung-Che, Fu, Chin-Ming, Wang, Wei-Hsiang, Kuo, Fred, Chang, Chih-Hsien, Hsieh, Kenny, Tam, King-Ho, Huang, Tze-Chiang, Chen, Tom, Wong, Mei, Changchien, Wei-Pin, Lee, Frank

“…This work presents a power impedance measurement (PIM) architecture for the 3D-IC platform with high-performance computing (HPC) applications. Proposed…”
Get full text

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4 by Lin, Mu-Shan, Tsai, Chien-Chun, Li, Shenggao, Huang, Tze-Chiang, Huang, Wen-Hung, Huang, Kate, Chen, Yu-Chi, Liu, Alex, Huang, Yu-Jie, Wang, Jimmy, Yang, Shu-Chun, Cheng, Nai-Chen, Li, Chao-Chieh, Kuo, Hsin-Hung, Chen, Wei-Chih, Wen, C.H., Lin, Kevin, Huang, Po-Yi, Hsieh, Kenny Cheng-Hsiang, Lee, Frank

“…This paper presents a die-to-die link with a compute die in 5nm FinFET and a SRAM die in 6nm FinFET, with a face-to-back 3D stacking at a 9μm bond pitch…”
Get full text

A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS by Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Hsieh, Kenny, Chen, Mark

“…This paper presents a low-jitter PLL with a wide operating range of 0.5~4GHz using proposed soft-injection technique. Its ring-type VCO with built-in PSRR of…”
Get full text

A 56-Gb/s Long-Reach Fully Adaptive Wireline PAM-4 Transceiver in 7-nm FinFET by Pfaff, Dirk, Goh, Tae Young, Wang, Xin-Jie, Palusa, Chai, Abbott, Robert, Moazzeni, Shahaboddin, Gao, Leisheng, Chuang, Mei-Chen, Ramirez, Rolando, Amer, Maher

“…This letter presents a 56-Gb/s PAM-4 transceiver which achieves a bit error rate of 2×10 -9 through -33 dB of channel insertion loss while consuming 500-mW…”
Get full text

Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS by Savoj, Jafar, Aslanzadeh, Hesam, Carey, Declan, Erett, Marc, Fang, Wayne, Frans, Yohan, Hsieh, Kenny, Im, Jay, Jose, Anup, Turker, Didem, Upadhyaya, Parag, Wu, Daniel, Chang, Ken

“…This paper describes the design techniques to achieve wideband flexible-reach operation in a fully-adaptive transceiver embedded in a 20nm CMOS FPGA. The…”
Get full text

19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications by Li, Chao-Chieh, Yuan, Min-Shueh, Chang, Chih-Hsien, Lin, Yu-Tso, Liao, Chia-Chun, Hsieh, Kenny, Chen, Mark, Staszewski, Robert Bogdan

“…Energy harvesting (EH) is a topic of intensive research promising battery-free operation of massive networks of wireless IoT devices. To simultaneously satisfy…”
Get full text

Design of high-speed wireline transceivers for backplane communications in 28nm CMOS by Savoj, J., Hsieh, K., Upadhyaya, P., Fu-Tai An, Im, J., Xuewen Jiang, Kamali, J., Kang Wei Lai, Wu, D., Alon, E., Ken Chang

“…This paper describes the design of the architecture and circuit blocks for backplane communication transceivers. A channel study investigates the major…”
Get full text

A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications by Lu, Tsung-Che, Fu, Chin-Ming, Liao, Chia-Chun, Lin, Yu-Tso, Chang, Chih-Hsien, Hsieh, Kenny

“…This work shows a system for power delivery network (PDN) impedance measurements (PIM), targeting high-performance computing (HPC) applications. A delay-line…”
Get full text

A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET by Pfaff, Dirk, Moazzeni, Shahaboddin, Gao, Leisheng, Chuang, Mei-Chen, Wang, Xin-Jie, Palusa, Chai, Abbott, Robert, Ramirez, Rolando, Amer, Maher, Huang, Ming-Chieh, Lin, Chih-Chang, Kuo, Fred, Chen, Wei-Li, Goh, Tae Young, Hsieh, Kenny

“…This 56Gb/s PAM-4 transceiver leverages the high logic density provided by the 7nm FinFET technology through rigorous application of digital design styles: An…”
Get full text

A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS by Ko, Chen-Ting, Kuan, Ting-Kuei, Shen, Ruei-Pin, Chang, Chih-Hsien, Hsieh, Kenny, Chen, Mark

“…This paper presents a phase-locked loop that employs a track-and-hold charge pump and automatic loop gain control to enhance the jitter and spur performance…”
Get full text

A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS by Chen, Wei-Chih, Wen, Chin-Hua, Fu, Chin-Ming, Tsai, Tsung-Hsien, Chen, Yu-Chi, Huang, Wen-Hung, Tsai, Chien-Chun, Loke, Alvin L. S., Kenny, C. H.

“…We present a high-accuracy wideband quadrature clock generator (QCG) built in 5nm finFET CMOS. To achieve low power and high bandwidth, we employ an active…”
Get full text

A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS by Ting-Kuei Kuan, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Hsieh, Kenny, Chen, Mark

“…This paper presents a digital bang-bang phase-locked loop that employs background injection timing calibration and automatic loop gain control to enhance the…”
Get full text