Search Results - "Hsiao, M.S."

New techniques for untestable fault identification in sequential circuits by Syal, M., Hsiao, M.S.

“…This paper presents two low-cost fault-independent techniques that can be used to identify significantly more untestable faults than could be identified by…”
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An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection by Xiaoding Chen, Hsiao, M.S.

“…We present a novel scan architecture for simultaneously reducing test application time and test power (both average and peak power). Unlike previous works…”
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Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking by Weixin Wu, Hsiao, M.S.

“…We present a novel technique on mining relationships in a sequential circuit to discover global constraints. We utilize domain knowledge to prune the search…”
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A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage by Liang Zhang, Ghosh, I., Hsiao, M.S.

“…This paper presents a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The…”
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A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal by Qingwei Wu, Hsiao, M.S.

“…We present a new logic-simulation-based algorithm on verifying safety properties of large sequential hardware designs. This algorithm explores the search space…”
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Testing embedded sequential cores in parallel using spectrum-based BIST by Chen, X., Hsiao, M.S.

“…We present a new BIST (built-in-self-test) architecture for system-on-a-chip (SOC), which can test a cluster of embedded sequential cores simultaneously. The…”
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State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation by Qingwei Wu, Hsiao, M.S.

“…This paper presents a new algorithm to extract characteristic flip-flops, which form a characteristic state set, using state-correlation information. The…”
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ALAPTF: a new transition fault model and the ATPG algorithm by Gupta, P., Hsiao, M.S.

“…The work presents a new transition fault model called as late as possible transition fault (ALAPTF) model. The model aims at detecting smaller delays, which be…”
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Peak power estimation of VLSI circuits: new peak power measures by Hsiao, M.S., Rudnick, E.M., Patel, J.H.

“…New measures of peak power are proposed in the context of sequential circuits, and an efficient automatic procedure is presented to obtain very good lower…”
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Crystal Orientation Change and Its Origin in One-Dimensional Nanoconfinement Constructed by Polystyrene-block-poly(ethylene oxide) Single Crystal Mats by Hsiao, Ming-Siao, Zheng, Joseph X, Leng, Siwei, Van Horn, Ryan M, Quirk, Roderic P, Thomas, Edwin L, Chen, Hsin-Lung, Hsiao, Benjamin S, Rong, Lixia, Lotz, Bernard, Cheng, Stephen Z. D

“…Utilizing crystalline−amorphous block copolymers, such as in the case of polystyrene-block-poly(ethylene oxide) (PS-b-PEO), under a large amplitude shear…”
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Poly(ethylene oxide) Crystallization within a One-Dimensional Defect-Free Confinement on the Nanoscale by Hsiao, Ming-Siao, Chen, William Y, Zheng, Joseph X, Van Horn, Ryan M, Quirk, Roderic P, Ivanov, Dimitri A, Thomas, Edwin L, Lotz, Bernard, Cheng, Stephen Z. D

“…A new approach was designed to study polymer crystallization in a one-dimensional (1D), defect-free, nanoscale confinement utilizing single crystals of…”
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A novel transition fault ATPG that reduces yield loss by Liu, X., Hsiao, M.S.

“…In this article, we have presented a novel constrained broadside transition ATPG algorithm to avoid overtesting functionally (sequentially) untestable…”
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Success-driven learning in ATPG for preimage computation by Sheng, S., Hsiao, M.S.

“…Unbounded model checking fundamentally requires either image or preimage calculations. We introduce a hybrid method for making preimage calculations using ATPG…”
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An ant colony optimization technique for abstraction-guided state justification by Min Li, Hsiao, M.S.

“…In this paper, a novel heuristic for abstraction-guided state justification is proposed based on ant colony optimization (ACO). A probabilistic state…”
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Efficient Design Validation Based on Cultural Algorithms by Weixin Wu, Hsiao, M.S.

“…We introduce a new semiformal design validation framework to justify hard-to-reach corner-case states. We propose a cultural learning technique to identify the…”
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A Study of Implication Based Pseudo Functional Testing by Syal, M., Chandrasekar, K., Vimjam, V., Hsiao, M.S., Yi-Shing Chang, Chakravarty, S.

“…This paper presents a study of the implication based functional constraint extraction techniques to generate pseudo functional scan tests. Novel algorithms to…”
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Simulation-Directed Invariant Mining for Software Verification by Xueqi Cheng, Hsiao, M.S.

“…With the advance of SAT solvers, transforming a software program to a prepositional formula has generated much interest for bounded model checking of software…”
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Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility by Chandrasekar, M., Hsiao, M.S.

“…Silicon Diagnosis is the process of locating potential defect sites (candidates) in a defective chip. These candidates are then used as an aid during physical…”
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Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time by Hsiao, M.S., Banga, M.

“…Scan-based DFT is the de-facto industrial practice for testing integrated circuits (ICs). Variations in the scan architecture to improve test metrics have been…”
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Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking by Vimjam, V.C., Hsiao, M.S.

“…In this paper, we propose low-cost static deduction techniques by combining binary resolution and static logic implications to efficiently extract invariant…”
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