Delay and Power Optimization in VLSI Circuits

Delay and Power Optimization in VLSI Circuits

The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macro-models are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.

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Bibliographic Details
Published in:21st Design Automation Conference Proceedings pp. 529 - 535
Main Authors: Glasser, L.A., Hoyte, L.P.J.
Format: Conference Proceeding
Language:English
Published: IEEE 1984
Subjects:
Circuit optimization
Delay
Laboratories
Large scale integration
Macrocell networks
MOS devices
Power engineering computing
Programmable logic arrays
Silicon
Very large scale integration
Online Access:Get full text
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Description
Summary:The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macro-models are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.
ISBN:0818605421
9780818605420
ISSN:0738-100X
DOI:10.1109/DAC.1984.1585848